IBM CPC700 User Manual page 13

Tables
Table 1. Address Map 1-6
Table 2. PLL Usage 1-10
Table 3. Processor Interface Register Addressing 3-2
Table 4. Offsets for Processor Interface Registers 3-2
Table 5. CPC700 Address Map - Processor View 3-3
Table 6. CPC700 Address Map - PCI View 3-4
Table 7. Supported Processor Transfer Type Encodings/Response 3-5
Table 8. CPC700 Response for processor to System Memory Transactions 3-7
Table 9. Processor to Memory Cycle Translation 3-7
Table 10. PLB Master Cycles 3-8
Table 11. CPC700 Response to Processor Transactions to the PLB 3-8
Table 12. Processor to PLB Cycle Translation 3-10
Table 13. CPC700 Response to Processor Address Only Cycles 3-11
Table 14. Processor Address Bus Arbitration 3-11
Table 15. Processor Snoop Transfer Types 3-12
Table 16. PLB to Memory Cycle Translation 3-17
Table 17. Processor Interface Response to PLB Transactions 3-18
Table 18. Processor I/F Config Registers Indirect Access Register 3-19
Table 19. CPC700 Response to Processor Interface Configuration Transactions 3-19
Table 20. Valid Address, TBST_N, and TSIZ Combinations 3-20
Table 21. Memory Controller Register Addressing 4-3
Table 22. Offsets for Memory Controller Registers 4-3
Table 23. Determining Maximum Page Size 4-5
Table 24. SDRAM Memory Timing Parameters 4-6
Table 25. SDRAM Configuration Registers 4-8
Table 26. Mode Set Command Vector 4-13
Table 27. ROM Response to Memory Controller Read Cycles 4-30
Table 28. ROM Response to Memory Controller Write Cycles 4-30
Table 29. Processor Address to ROM Address Mapping 4-31
Table 30. Device Attachment to ROM/Peripheral Bus 4-32
Table 31. ROM Configuration Registers 4-32
Table 32. ECC Features 4-38
Table 33. ECC Registers 4-39
Table 34. ECC Enable and Correction Bits 4-40
Table 35. Effect of ECC on Timing 4-40
Table 36. Local Processor to Memory Controller Data Flow 4-41
Table 37. Local processor to PCI Data Flow 4-42
Table 38. PCI to Memory Controller Data Flow 4-42
Table 39. PCI Interface Local Configuration Registers 5-3
Table 40. PCI Interface Configuration Register Offsets 5-3
Table 41. PLB Address Map 5-5
Table 42. PCI Memory Address Map 5-7
Table 43. PCI Interface Responses to PCI Requests 5-11
Table 44. PCI interface Responses to PLB Requests 5-15
Table 45. Collision Resolution 5-17
Table 46. PCI Frequency Modes 5-18
CPC700 User's Manual-Preliminary xiii