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Bit
Name
0
UART0_RST
1
UART1_RST
2
IIC0_RST
3
IIC1_RST
4
GPT_RST
5
GPT_TBC_RST
6:31
6.5.3 GPT Capture Event Generation Register (CPRCAPTEVNT)
Address:
FF50_0908h
Width:
32 bits
Reset Value:
0000_0000
Access:
Read/Write
The General Purpose Timers (GPT) may be programmed to capture and time events. The GPT Event Gen-
eration Register may be used to signal capture events to the GPT. Each bit may be used to trigger one of
the five capture event timers. The value that these bits need to be set to trigger a capture event, is depen-
dent on the value of the GPT Edge Detection Control register in the GPT. They can be made falling-edge
active (set to 0 to trigger) or rising-edge active (set to 1 to trigger). Refer to Chapter 9., "General Purpose
Timers" for additional information. After triggering an event, these bits must be reset to their non-active val-
ues before another capture event can be triggered. When enabled in the CPC700's interrupt controller,
these events can be used to interrupt the processor.
.
Bit
Name
0
GPTEVNT0
1
GPTEVNT1
2
GPTEVNT2
3
GPTEVNT3
4
GPTEVNT4
5:31
CPC700 User's Manual—Preliminary
Table 65. Peripheral Reset Control Register
Default
Description
0
UART 0 Reset
0 - Deactivate UART 0 Reset
1 - Activate UART 0 Reset
0
UART 1 Reset
0 - Deactivate UART 1 Reset
1 - Activate UART 1 Reset
0
IIC 0 Reset
0 - Deactivate IIC 0 Reset
1 - Activate IIC 0 Reset
0
IIC 1 Reset
0 - Deactivate IIC 1 Reset
1 - Activate IIC 1 Reset
0
General Purpose Timer Reset
0 - Deactivate GPT Reset
1 - Activate GPT Reset
0
General Purpose Timer Time Base Counter Reset
0 - Deactivate GPT TBC Reset
1 - Activate GPT TBC Reset
0
Reserved - Read returns 0
Table 66. GPT Event Generation Register
Default
Description
0
Generate event to event timer 0
0
Generate event to event timer 1
0
Generate event to event timer 2
0
Generate event to event timer 3
0
Generate event to event timer 4
0
Reserved - read returns 0
6-7
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