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7.2.1.2 Line Status Register
Information concerning the data transfer is held for the processor in this register. Bits 3 through 6 are
conditions that produce a receiver line status interrupt whenever the condition corresponding to the active
bit is detected and the interrupt is enabled. This register is intended for read operations only and writing is
not recommended.
Bit #
Value
0
0
1
1
0
1
2
0
1
3
0
1
4
0
1
5
0
1
7-6
Table 73. Line Status Register Description
Receiver FIFO Error indicator. Always 0 in 16450 mode. In FIFO mode, it is reset to 0 whenever the
processor reads the LSR, provided there are no subsequent errors in the FIFO.
Receiver FIFO Error indicator. Set to 1 when there are one or more instances of parity error, framing
error or break indication in the FIFO.
Transmitter empty (TEMT) indicator. Reset to logic 0 whenever the THR or the transmitter shift
register contain a character. In FIFO mode, it is reset to logic 0 whenever the transmitter FIFO or the
transmitter shift register contain a character.
Transmitter empty (TEMT) indicator. Set to logic 1 when the THR and the Transmitter shift register
are both empty. In FIFO mode, it is set to logic 1 when the transmitter FIFO and the transmitter shift
register are both empty.
Transmitter holding register empty (THRE) indicator. Concurrent reset to 0 with the loading of the
THR by the processor. In FIFO mode it is reset to 0 when at least one byte is written to the
transmitter FIFO.
Transmitter holding register empty (THRE) indicator. Logic 1 when the UART is ready to accept a
new character for transmission. When the THRE enable (bit 6 in the IER) is set to logic 1, the UART
will issue an interrupt to the CPC700 interrupt controller. This bit is set to logic 1 when a character is
transferred from the THR to the transmitter shift register. In FIFO mode, this bit is set when the
transmitter FIFO is empty.
Break interrupt (BI) indicator. Reset to 0 whenever processor reads LSR.
Break interrupt (BI) indicator. Set to logic 1 whenever the received data input is held at the spacing
level (logic 0) for longer than a full word transmission time. The full word transmission time is the time
required for the start bit, data bits (can be 5-8 bits), parity and stop bits. In FIFO mode, this error is
revealed to the processor when the character this error is associated with is at the top of the FIFO.
Only one zero character is loaded into the receiver FIFO when a break occurs. After the next valid
start bit is received and has gone into the marking state, the next character transfer is enabled.
Framing error (FE) indicator. Reset to 0 whenever processor reads LSR.
Framing error (FE) indicator. Indicates that a valid stop bit was not found in the received character.
Set to logic 1 whenever stop bit following the last data bit or parity bit is detected as logic 0 (spacing
level). In FIFO mode, this error is revealed to the processor when the character this error is
associated with is at the top of the FIFO. To resynchronize after a framing error, the UART will
assume that the framing error was due to the next start bit, so it will sample this "start bit" twice, then
take in the data.
Parity error (PE) indicator. Reset to 0 whenever processor reads LSR.
Parity error (PE) indicator. Indicates that the received data character does not have the correct parity
as determined by the even parity select bit of the LCR. Set to logic 1 upon detection of a parity error.
In FIFO mode, this error is revealed to the processor when the character this error is associated with
is at the top of the FIFO.
LSR Bits
Description
UART
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