Aborted Plb Requests - IBM CPC700 User Manual

Table 44.PCI interface Responses to PLB Requests (Continued)
PLB Direction PCI Address
and Size Space
read burst, any memory, I/O,
size configuration or
int. ack.
write, 1-4 byte memory, I/O,
configuration,
special cycle
write, 1-4 byte memory, I/O
write, 1-4 byte memory, I/O
write, 1-4 byte configuration or
special cycle
write, 1-4 byte configuration or
special cycle
write, burst memory, I/O,
configuration,
special cycle
write, line, any memory I/O,
size configuration,
special cycle

5.7.4.1 Aborted PLB Requests

There are only two case where a PLB master accessing the PCI interface is allowed to abort the PLB
cycle.
1. The PCI interface rearbitrates the cycle.
2. The PCI interface does not see the cycle because the PLB bus is granted to some other master. A
Processor/System Memory interface is expected to do this when a processor cycle is pending to the
PCI interface, but a PLB Master requests system memory access requiring snooping.
5-16
PLB, PCI Bus PCI Response
Action
PLB: none (not sup- n/a
ported)
PCI: none
PLB: assert master/target
Sl[x]_wait abort
PCI: request bus
PLB: complete retry or discon-
transaction (post) if nect
buffer available
PCI: request bus
PLB: complete accept
transaction (post) if
buffer available
PCI: request bus
PLB: assert retry
Sl[x]_wait
PCI: request bus
PLB: assert accept or dis-
Sl[x]_wait connect
PCI: request bus
PLB: none (not sup- n/a
ported)
PCI: none
PLB: none (not sup- n/a
ported)
PCI: request bus
PCI interface Action
none
complete PLB cycle
with Sl[x]_MErr
re-request PCI bus
complete PCI trans-
action; deallocate
buffer
rearbitrate PLB
complete PCI trans-
fer; complete PLB
transfer
none
none
PCI Interface