Table 2. Pll Usage - IBM CPC700 User Manual

Universal Interrupt Controller (UIC)
The Universal Interrupt Controller (UIC) provides the control, status, and communications necessary
between the various sources of interrupts and the local PowerPC processor. Features of the UIC include
the following:
• 29 interrupt sources.
- 12 external interrupts.
- 10 timer interrupts - five compare and five event capture.
- Two UART interrupts.
- Two IIC interrupts.
- PCI access to config register interrupt.
- PCI access to local memory interrupt.
- ECC correctable error interrupt.
• Interrupts are individually maskable.
• Interrupts can be individually programmed to generate a Machine Check Exception (MCP) or an Exter-
nal Interrupt (INT) to the processor.
• Interrupt types supported.
- Synchronous level sensitive.
- Synchronous edge-capture.
- Asynchronous- Choice of edge or level sensitive triggering is programmable.
• Polarity is programmable for all types.
• Prioritized interrupt handler vector generation.
• Status registers provide both of the following for interrupts.
- Current state of interrupts.
- Current state of all enabled interrupts (masked with Enable register).
Phase Locked Loop (PLL)
PLL Input Frequency
PLL 0 33MHz
PLL 1 25MHz to 66MHz
The CPC700 clocking is controlled by two PLLs that minimize clock skew between the internal latches of
the CPC700 and the external devices in the system. PLL1 is only used when the PCI interface is used in
asynchronous mode. When in synchronous mode, PLL1 is placed in bypass mode via pin strappings, and
the PCI clock input pin must be pulled to ground.
1-10

Table 2. PLL Usage

Output Frequency
33MHz
66MHz
Same as input
Usage
UART, IIC, and Timers
All Other Cores
Async PCI Interface
CPC700 User's Manual—Preliminary