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7.2.1 UART Register Summary
The system programmer may access any of the UART registers summarized in Table 71. via the
processor. These registers control the UART operations including transmission and reception of data. Each
register bit in the table has its name and reset state shown.
Table 71. Summary of UART Registers (Big Endian Notation)
A
d
d
Register
r
Name
e
s
a
s
Receiver Buffer
0000
RBR
Register (read only)
Transmitter Holding
0000
THR
Register (write only)
Interrupt Enable
0001
IER
Register (read and
write)
Interrupt Identification
X010
IIR
Register (read only)
FIFO Control Register
X010
FCR
(write only)
Line Control Register
X011
LCR
(read and write)
Modem Control
X100
MCR
Register (read and
d
write)
Line Status Register
X101
LSR
(read and write)
Scratch Register (read
X111
SCR
and write)
Divisor Latch (LSB)
1000
DLL
(read and write)
Divisor Latch (MSB)
1001
DLM
(read and write)
a. DLAB concatenated with LTADR2 through LTADR0.
b. Bit 7 is the least significant bit (lsb). It is the first bit serially transmitted and received.
c. This bit is always zero in character mode.
d. The only valid bit of the MCR in this two-wire implementation of the UART is MCR bit 4, the Loopback Mode bit, which can be used for diagnostic purposes.
Note: Register bit definitions are shown in big-endian notation. (bit 7 is lsb and bit 0 is msb.)
7-4
A
l
i
0
1
a
s
Data
Data
Bit 0
Bit 1
Data
Data
Bit 0
Bit 1
0
0
FIFOs
FIFOs
Enabled
Enabled
RCVR
RCVR
Trigger
Trigger
(MSB)
(LSB)
Divisor
Set Break
Latch
Access
Bit
(DLAB)
Reserved
Reserved
Error in
TransmitterE
Receiver
mpty
FIFO
(TEMT)
Data
Data
Bit 0
Bit 1
Data
Data
Bit 8
Bit 9
Data
Data
Bit 0
Bit 1
Function of Each Bit
2
3
4
Data
Data
Data
Bit2
Bit 3
Bit 4
Data
Data
Data
Bit 2
Bit 3
Bit 4
0
0
0
0
0
InterruptID
c
Bit 2
Reserved
Reserved
DMA
Mode
Select
Stick Parity
Even
Parity
Parity
Enable
Select
(PEN)
(EPS)
Reserved
Reserved
Loopback
Mode
Transmitter
Break
FramingErr
Holding
Interrupt
or
Register
(BI)
(FE)
(THRE)
Data
Data
Data
Bit2
Bit 3
Bit 4
Data
Data
Data
Bit 10
Bit 11
Bit 12
Data
Data
Data
Bit 2
Bit 3
Bit 34
5
6
Data
Data
Data
Bit 5
Bit 6
Bit 7
Data
Data
Data
Bit 5
Bit 6
Bit 7
Enable
Enable
Enable
Receiver
Transmitter
Receive
Line
Holding
Data
Status
Register
Available
Interrupt
Empty
Interrupt
(ELSI)
Interrupt
(ERDAI)
(ETHREI)
Interrupt ID
Interrupt
"0" if
Bit 1
ID
Interrupt
Bit 0
Pending
XMIT
RCVR
FIFO
FIFO
FIFO
Enable
Reset
Reset
Number
Word
Word
of Stop
Length
Length
Bits
Select
Select
(STB)
Bit 1 (WLS1)
Bit 0
(WLS0)
Reserved
Reserved
Reserved
Parity
Overrun Error
Data
Error
(OE)
Ready
(PE)
(DR)
Data
Data
Data
Bit5
Bit6
Bit 7
Data
Data
Data
Bit 13
Bit 14
Bit 15
Data
Data
Data
Bit 5
Bit 6
Bit 7
UART
7
b
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