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The Bridge Options 2 register controls various operating parameters of the PCI Bridge. Descriptions of
each bit are shown in Table 58.
Bit(s)
Name
0
Host Config Enable
1
Reserved
2
PCI Discard Timer
Disable
7:3
PCI Initial Target
Latency Timer Dura-
tion
11:8
PCI Subsequent Tar-
get Latency Timer
Duration
12
Drive PCI Reset
13
External Write to PCI
Command Interrupt
15:14
Reserved
Note:
1.
The Maximum Initial Target Latency (MITL) is the maximum number of clocks from the assertion
of FRAME# to the first assertion of either TRDY# or STOP#.
5.9.3.34 PCI Initial Target Latency Timer Duration
When in synchronous mode, the value of this field directly determines the Maximum Initial Target Latency
(MITL). When in asynchronous mode, the value of this register plus 14 determines the MITL.
In both synchronous and asynchronous modes, the cycle may be retried (or data returned) before the
MITL has passed. In asynchronous mode, the cycle is typically retried within the value of this register plus
5 (plus 14 is the worst case).
The minimum number of clocks from the assertion of FRAME# to the first assertion of either TRDY# or
STOP# is two clocks (medium DEVSEL# speed). Setting this register to a value of 0 or 1 produces the
same results as setting it to 2 (even in asynchronous mode).
5-42
Table 58.Bridge Options 2 Register Bits
Description
This bit controls Host PCI access to the PCI Configuration regis-
ters. This bit is 0 at reset, thus all Host attempts to access the
CPC700's PCI configuration registers are retried. This give the
local CPU (PLB master) time to initialize them before the Host sees
them.
When 1, this bit disables the PCI Target latency timer. This pre-
vents the use of the Delayed Read mechanism.
When 1, the CPC700 will never discard Delayed Read data.
Determines the Maximum Initial Target Latency (MITL).
Refer to Section 5.9.3.34 "PCI Initial Target Latency Timer Dura-
tion" .
Determines the number of PCI clocks that a PCI master burst can
be held in a wait state (only occurs on reads) before a target dis-
connect is initiated. Refer to Section 5.9.3.35 "PCI Subsequent
Target Latency Timer Duration" .
When high, causes PCI_RST# pin to be asserted (PCI_RST# is
also asserted when PLB_SYSReset is asserted). Software that
asserts this bit must leave it asserted long enough to guarantee
the PCI pulse width requirements. The PLB bus interface and reg-
ister sets of the PCI Bridge are NOT reset by this bit.
When an external PCI master writes to the PCI Command register,
this bit is set and an interrupt is generated to the CPC700 interrupt
controller (IRQ 2).
Reserved, always read as 0.
1
PCI Interface
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