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4.5.1 Initialization Sequence
The SDRAM must be initialized prior to being accessed. This is accomplished through a combination of
System and SDRAM Controller actions as follows:
System:
1.
After Reset is deactivated, pause the amount of time indicated in the SDRAM specification.
- Example: IBM 16MB SDRAM requires 100us pause and 64MB SDRAM requires 200us.
2.
Configure SDRAM related configuration registers (may occur during pause period).
3.
Set DC_EN = 1 in the MCOPT1 register to enable the SDRAM controller
Step 3 automatically causes the SDRAM Controller to:
1.
Issue Precharge command to all banks.
2.
Wait minimum defined by SD_PTA bits in the SDTR1 register.
3.
Perform eight CBR refresh cycles (each separated by SD_RFTA clock cycles).
4.
Issue Mode Register Write Command.
5.
Perform eight CBR refresh cycles (each separated by SD_RFTA clock cycles).
6.
Wait SD_RFTA clock cycles.
7.
Be available for access.
4.5.2 Page Mode Accesses
The SDRAM page size for all supported addressing modes is 2K for 32-bit (40-bit ECC) memories (1K for
mode-4), and 4K for 64-bit (72-bit ECC) memories (2K for mode-4). Pipelined accesses to system memory
from the local processor or PCI which address the same page within a given memory bank are treated as
page hits provided that the addressed bank is active when the pipelined access request is forwarded to the
SDRAM controller.
Accesses which Page Miss/Bank Miss take advantage of the precharge state of the newly selected bank
by driving the ROW address and activating the new bank. The previously accessed bank is precharged.
SDRAM memory subsystem implementations contain banks and sub-banks. A bank corresponds to a
SDRAM chip select while the sub-banks correspond to SDRAM bank addresses. Within the context of the
above discussion, Bank Miss may be either a bank or sub-bank miss.
Note: Page size is independent of the actual vendor SDRAM column address geometry. This can be seen
by examining the Memory Mapping tables in the following sections. Notice that there are only 9 contiguous
column address bits for modes 1-3, and 8 for mode 4. Table 23. summarizes the factors that control the
actual page size:
mode 1-3
32-bit
contiguous column address bits = 9
9
(40-bit ECC)
2
=512 unique column addresses
data width 32-bit = 4 byte
page size = 512 x 4byte = 2KByte
CPC700 User's Manual—Preliminary
Table 23. Determining Maximum Page Size
mode 4
contiguous column address bits = 8
8
2
=256 unique column addresses
data width 32-bit = 4 byte
page size = 256 x 4byte = 1KByte
4-5
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