IBM CPC700 User Manual page 144

Table 43.PCI Interface Responses to PCI Requests (Continued)
PCI Transaction PLB Size
memory read single-beat read
memory read line word burst read
or memory read
multiple
memory read line word burst read
or memory read
multiple
memory read line word burst read
or memory read
multiple
Read buffer hit on n/a
memory read,
memory read line
or memory read
multiple
memory write, sin- single-beat write,
gle-beat 1-4 byte
memory write, sin- single-beat write,
gle-beat 1-4 byte
memory write, word burst write
burst or memory
write and invali-
date
memory write, burst write
burst or memory
write and invali-
date
memory write, burst write
burst or memory
write and invali-
date
5-12
PCI, PLB Bus
Action
PCI: DEVSEL_
PLB: request bus
1
PCI: DEVSEL_
PLB: request bus
1
PCI: DEVSEL_
PLB: request bus
1
PCI: DEVSEL_
PLB: request bus
PCI: DEVSEL_
PLB: none
PCI: complete
2
transaction(post)
PLB: request bus
PCI: complete
2
transaction(post)
PLB: request bus
2,3
PCI: complete
transaction(post)
PLB: request bus
2,3
PCI: complete
transaction(post)
PLB: request bus
2,3
PCI: complete
transaction(post)
PLB: request bus
PLB Response PCI Interface
Action
PLB_M[x]Rearbi- retry PCI
trate
PLB_M[x]AddrAck transfer PCI burst
data
PLB_M[x]RdB- Re-request PLB if
Term buffer becomes
half empty
PLB_M[x]Rearbi- retry PCI
trate
n/a source read data
to PCI. Request
PLB read
(prefetch) if read
multiple and buffer
becomes half
empty
PLB_M[x]AddrAck transfer data to
(of posted write PLB
request)
PLB_M[x]Rearbi- re-request PLB
trate (of posted
write request)
PLB_M[x]AddrAck burst data to PLB
(of posted write
request)
PLB_M[x]wrB- increment buffer
Term address; re-
request PLB
PLB_M[x]Rearbi- re-request PLB
trate
PCI Interface