Memory Controller Registers; Table 21. Memory Controller Register Addressing; Table 22. Offsets For Memory Controller Registers - IBM CPC700 User Manual

4.3 Memory Controller Registers

The memory controller registers are accessed through an indirect method employing a configuration
address register, MEMCFGADR, and a configuration data register, MEMCFGDATA. To access one of the
memory controller registers, write the appropriate index to register MEMCFGADR, then read the data from
or write the data to register MEMCFGDATA. All configuration accesses from the processor must be 4 Byte
aligned, otherwise an error will be generated and the cycle not performed.
Register
MEMCFGADR
MEMCFGDATA
Table 22 lists the offsets for the various configuration registers located within the memory controller.
Register
MCOPT1
MBEN
MEMTYPE
RWD
RTR
DAM
MB0SA
MB1SA
MB2SA
MB3SA
MB4SA
MB0EA
MB1EA
MB2EA
MB3EA
MB4EA
SDTR1
RBW
FWEN
ECCCF
CPC700 User's Manual—Preliminary

Table 21. Memory Controller Register Addressing

Address R/W Description
FF50_0008 R/W Memory Controller Configuration Address Register
FF50_000C R/W Memory Controller Configuration Data Register

Table 22. Offsets for Memory Controller Registers

Offset R/W
20 R/W
24 R/W
28 R/W
2C R/W
30 R/W
34 R/W
38 R/W
3C R/W
40 R/W
44 R/W
48 R/W
58 R/W
5C R/W
60 R/W
64 R/W
68 R/W
80 R/W
88 R/W
90 R/W
94 R/W
Description
Memory Controller Options 1
Memory Bank Enable
Installed Memory Type
Bank Active Watchdog Timer
Refresh Timer Register
DRAM Addressing Mode
Memory Bank 0 Starting Address
Memory Bank 1 Starting Address
Memory Bank 2 Starting Address
Memory Bank 3 Starting Address
Memory Bank 4 Starting Address
Memory Bank 0 Ending Address
Memory Bank 1 Ending Address
Memory Bank 2 Ending Address
Memory Bank 3 Ending Address
Memory Bank 4 Ending Address
SDRAM Timing register 1
ROM Bank Width
Flash Write Enable
ECC Configuration
4-3