Memory Controller Registers - IBM CPC700 User Manual

Table 103. Offsets for Processor Interface Registers (Continued)
Register
BESRSET
Reserved
BEAR
Reserved
Reserved
PLBSWRINT

14.1.2 Memory Controller Registers

The Memory controller registers are accessed similar to the processor interface registers through an indi-
rect address mechanism. The table below lists the indirect address and data registers for accessing the
memory controller.
Register
MEMCFGADR
MEMCFGDATA
The following table lists the offsets for the various configuration registers located within the memory con-
troller. See Section 4.9, "Memory Controller Register Description" for detailed register information.
Register
MCOPT1
MBEN
MEMTYPE
RWD
RTR
DAM
MB0SA
MB1SA
MB2SA
MB3SA
MB4SA
14-2
Offset R/W Description
44 W PLB Bus Error Syndrome Register Set (for test/verification
use)
48
4C R/W PLB Bus Master Error Address Register
50
54
80 R/W Write Interrupt Region Base Address
Table 104. Memory Controller Register Addressing
Address R/W Description
FF50_0008 R/W Memory Controller Configuration Address Register
FF50_000C R/W Memory Controller Configuration Data Register
Table 105. Offsets for Memory Controller Registers
Offset R/W
20 R/W
24 R/W
28 R/W
2C R/W
30 R/W
34 R/W
38 R/W
3C R/W
40 R/W
44 R/W
48 R/W
Description
Memory Controller Options 1
Memory Bank Enable
Installed Memory Type
Bank Active Watchdog Timer
Refresh Timer Register
DRAM Addressing Mode
Memory Bank 0 Starting Address
Memory Bank 1 Starting Address
Memory Bank 2 Starting Address
Memory Bank 3 Starting Address
Memory Bank 4 Starting Address
Register Summary