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5.9.3.28 Error Status
Address offset: 49h
Width:
8
Reset Value:
00h
Access:
Read/Write
The Error Status register is an 8-bit read/write register which contains status on error conditions that have
been detected (see Table 55.). Bits in this register can only be set to 1 as a result of a system error occur-
ring. These bits can be reset by writing a 1 to the desired bit location. Writing a 0 to any bit leaves that bit
unchanged.
Bit(s)
Name
0
PLB Unsupported
Request
1
PCI_SERR# on Write
Data Parity Error
2
MErr Assertion Event
3
MErr Detected
4
SERR# Asserted on
Received MErr
7:5
Reserved
5.9.3.29 Bridge Options 1
Address offset: 4Bh-4Ah
Width:
16
Reset Value:
FF60h
Access:
Read/Write
5-38
Table 55.Error Status Resister Bits
Description
This bit is set when the PCI interface is a PLB slave and detects an
unsupported request from a PLB master to an address range that
the PCI interface decodes. the PCI interface allows such requests
to timeout.
This bit is set when the CPC700 drives PCI_SERR# (PCI_PERR#
is also driven) in response to a data parity error detected on a PCI
write to PLB memory.
This bit is set whenever an error occurs which would cause the PCI
interface (as PLB slave) to assert Sl[x]_MErr, regardless of
whether or not Sl[x]_MErr assertion is enabled. I.e. setting of this
bit is non-maskable.
This bit is set whenever PLB_MErr is asserted when the PCI inter-
face is the PLB master, regardless of whether or not the PCI inter-
face is enabled to treat this as an error condition, i.e. setting of this
bit is non-maskable.
This bit is set when the CPC700 asserts PCI_SERR# on the PCI
bus in response to the PCI interface receiving PLB_MErr while
PLB master.
These bits are reserved and return 0 when read.
PCI Interface
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