Byte Enable Handling; Pci Request Responses; Table 43.Pci Interface Responses To Pci Requests - IBM CPC700 User Manual

5.6.2.6 Byte Enable Handling

The PLB bus does not support non-contiguous byte enables, whereas the PCI bus does. Additionally, the
PLB only supports the use of byte enables for non-line, non-burst transactions, whereas the PCI bus sup-
ports any combination of byte enables for any data phase; therefore, when a PCI master presents a data
phase with not all byte enables asserted, the bridge must, in certain cases, take the following special
actions:
• When a PCI data phase with non-contiguous byte enables is detected, the CPC700 continues accept-
ing data (buffer space allowing), but that data phase is converted into two single beat, 1-2 byte PLB
writes, independent of previous PCI data phases. Note that the size of each PLB transaction will be at
most 2 bytes because that is the maximum size possible for a PCI data phase with non-contiguous
byte enables.
• When a PCI data phase with contiguous (but not all active) byte enables is detected, the CPC700 con-
tinues accepting data, but that data phase is converted into one single beat, 1-3 byte PLB write, inde-
pendent of previous PCI data phases. If no byte enables are active, the data phase in converted into a
single beat, and then eliminated. Note that the size of each PLB transaction will be at most 3 bytes
because that is the maximum size possible for a PCI data phase with contiguous but not all active byte
enables.
Example: A PCI master device executes an 8 beat write. The (active low) byte enables are driven thus:
0000, 0000, 0000, 0101, 0111, 0000, 0000, 1001. The PCI interface executes the following writes on PLB:
3-beat word burst; 3 successive single-beat, 1-byte writes; 2-beat burst write; 2-byte write.
This method of handling non-contiguous byte enables results in degraded performance on memory writes
when non-contiguous byte enables are used.

5.6.3 PCI Request Responses

Table 43. describes the PCI interface's response to PCI master commands. The PCI terms "retry" and "dis-
connect" refer to, respectively, transaction abort with no data transferred and transaction abort with at least
one beat of data transferred. A blind disconnect refers to one in which the PCI target disconnects concur-
rently with the PCI master's last data beat.
All actions listed in the "PCI Interface Actions" column are done in sequential order. The table assumes that
the PCI interface is initially in the idle state and has available buffer space.
PCI Transaction PLB Size
I/O, configuration n/a
read or write (no
IDSEL),
interrupt acknowl-
edge,
special cycle
memory read single-beat read
CPC700 User's Manual—Preliminary

Table 43.PCI Interface Responses to PCI Requests

PCI, PLB Bus
Action
none
PCI: assert
DEVSEL_
PLB: request bus
PLB Response PCI Interface
Action
n/a none
PLB_M[x]AddrAck transfer PCI data
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