Interrupt Enable Register - IBM CPC700 User Manual

Table 75. Interrupt Identification Register Description (Continued)
Bit # Value
Bit Bit
4 5
0 1
4, 5 and
6
0 1
1 1
0 0
0 0
0
7
1

7.2.1.5 Interrupt Enable Register

Three types of UART interrupts are enabled via the interrupt enable register (IER). Any of the three
interrupt types can be used to surface a UART interrupt to the CPC700 interrupt controller. Each interrupt
type can be enabled by setting its appropriate bit. Resetting bits 4 through 7 of the IER totally disables the
UART interrupt system. Disabling an interrupt prevents it from being shown as active in the IIR and
prevents it from signalling a UART interrupt to the CPC700 interrupt controller.
Bit # Value
0 0
Always 0
1 0
Always 0
2 0
Always 0
3 0
Always 0
4
reserved
CPC700 User's Manual—Preliminary
Bits 5 and 6 are used to indicate the interrupt priority as shown below. Bit 4 is always 0 in
16450 mode. In FIFO mode, when a timeout interrupt is pending, bits 4 and 5 are set to
logic 1.
Bit
Priority Interrupt Type
6
Level
1
1st Receiver Line
Status
0
2nd Received Data
Available
0
2nd Character timeout
Indication
1
3rd Transmitter Holding
Register Empty
0
reserved
Interrupt is pending. IIR contents may be used as a pointer to the appropriate interrupt
service routine.
No interrupt is pending.
Table 76. Interrupt Enable Register Description
IIR Bits
Description
Interrupt Source
Overrun, Parity or Framing
Error, or Break Interrupt
Receiver data available or
trigger level reached.
No characters have been
removed from or input to the
receiver FIFO during the last
four char. times and it
contains at least one char.
during this time.
Transmitter Holding Register
Empty
IER Bits
Description
Interrupt Reset
Control
Read LSR
Read RBR, or FIFO
drops below trigger
level.
Read RBR
Read IIR (if source
of interrupt) or write
THR
7-9