IBM CPC700 User Manual page 121

Memory controller and pci bridge
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Bit
Name
11
SD_SREX
12:13
SD_PTA
14:17
SD_WTP
18:21
SD_RTP
22:26
27:29
SD_RFTA
30:31
SD_RCD
CPC700 User's Manual—Preliminary
Reset
Description
Value
0
SDRAM Self-Refresh Exit delay.
Minimum number of clock cycles until first access allowed fol-
lowing self-refresh exit.
0 - 12 CLK
1 - Reserved
01
SDRAM Precharge Command to next Activate Command mini-
mum.
00 - Reserved
01 - 2 CLK
10 - 3 CLK
11 - 4 CLK
0010
SDRAM Write Command to Precharge Command minimum.
SDRAM Write with Auto-Precharge Command to Auto-Pre-
charge latency.
0000 - Reserved
0001 - 1111 Binary Decode (1 - 15 Clocks)
0111
SDRAM Read Command to Precharge Command minimum.
SDRAM Read with Auto-Precharge Command to Auto-Pre-
charge latency.
0000 - Reserved
0001 - 1111 Binary Decode (1 - 15 Clocks)
0s
Reserved
010
SDRAM CAS before RAS Refresh Command to next Activate
Command minimum.
000 - 4 CLK
001 - 5 CLK
010 - 6 CLK
011 - 7 CLK
100 - 8 CLK
101 - 9 CLK
110 - 10 CLK
111- Reserved
10
SDRAM RAS to CAS delay.
Indicates the number of clock cycles from Activate Command to
Read or Write Command.
0x - Reserved
10 - 2 CLK
11 - 3 CLK
4-49

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