IBM CPC700 User Manual page 25

The CPC700 UARTs are functionally identical to NS16450 in character mode (on power up they will be in
this mode). The UARTs can be put into FIFO mode to relieve the processor of excessive software over-
head. Here internal FIFOs are activated, allowing 16 bytes (plus three bits per byte of error data in the
RCVR FIFO) to be stored in both receive and transmit modes. The timing reference clock is the CPC700
SYS_CLOCK input divided by 4. This will generally be 8.333MHz in a typical application (PowerPC local
processor operating with a 66MHz bus frequency).
The UARTs include a programmable baud rate generator capable of dividing the timing reference clock by
16
a divisor of 1 to (2 -1), and they produce a 16x clock for driving the internal transmitter logic. This 16x
clock can also be used to drive the receiver logic.
The UARTs have a processor interrupt system. Interrupts can be programmed to the user's requirements,
minimizing the computing required to handle the communications link.
IIC Bus Interface
The CPC700 provides two fully independent IIC bus interfaces. The IIC bus is a two wire, bidirectional,
open-drain, low speed serial interface. Both the serial clock (SCL) and the serial data (SDA) lines are bidi-
rectional to support multiple bus masters and to mix "fast" and "slow" devices on the same bus. The
CPC700 IIC interfaces support the following standard and/or enhanced features of the Philips
2
ductors I C Specification , dated 1995:
• 100 or 400 kHz operation.
• 8-bit data.
• 10- or 7-bit address.
• Slave transmitter and receiver.
• Master transmitter and receiver.
• Multiple bus masters.
• Two independent 4x1 byte data buffers.
• 12 memory mapped and fully programmable configuration registers.
• One programmable interrupt request signal.
• Provides full management of all IIC bus protocol
General Purpose Timers (GPT)
The General Purpose Timer (GPT) provides a separate time base counter and system timers for the
CPC700. Five capture timers and five compare timers are implemented in the GPT macro. Features of the
GPT core include:
• 32-bit time base.
- Updated once every CPC700 SYS_CLOCK.
• Five capture event timers.
• Five compare timers.
• 10 interrupt outputs, one for each capture and compare timer.
CPC700 User's Manual—Preliminary
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