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2.5 System Interface Signals
Active
Signal Name
Level
SYS_CLOCK
—
SYS_RESET_N
Low
RESET_OUT_N
Low
IRQ[0:11]
High
IRQ_OUT_N
Low
SYSPLL_VDDA
High
PCIPLL_VDDA
High
2.6 Test Interface Signals
Active
Signal Name
Level
TDI
High
TMS
High
TDO
High
TCK
High
TRST_N
Low
TEST_ENABLE
High
CPC700 User's Manual—Preliminary
I / O
Description
I
System Clock Input: The system clock input must be one half the
frequency and in phase with the local processor and SDRAM clocks.
I
System Reset Input: Resets the CPC700 to its initial default state. The
internal reset will remain active for 500us after the SYS_RESET_N
signal is deasserted.
O
Reset Output: RESET_OUT_N follows the internal reset and will be
driven for 500us after the SYS_RESET_N signal is deasserted.
RESET_OUT_N will also be driven in the event that the PLL tuning bit
register is written so that the internal PLLs may re-lock with the new
configuration. After RESET_OUT_N is deasserted, the CPC700 will be
in its initial default state. The RESET_OUT_N signal should drive into
the processor's hard reset logic.
I
Interrupt Input [0:11]: Twelve external interrupts may be attached and
allowed to interrupt the processor. These interrupt inputs are
asynchronous and may be programmed to cause an interrupt on either
the rising or falling edge.
O
Interrupt Output: Interrupt output to the local processor.
I
System Clock PLL Analog Voltage Pin: The analog voltage pin for the
System PLL must be connected to a quiet voltage. Typically this voltage
should be isolated from the system digital voltage plane.
I
Async PCI Clock PLL Analog Voltage Pin: The analog voltage pin for
the asynchronous PCI PLL must be connected to a quiet voltage.
Typically this voltage should be isolated from the system digital voltage
plane.
I / O
Description
I
JTAG Test Data Input
I
JTAG Test Mode Select
O
JTAG Test Data Output
I
JTAG Test Clock
I
JTAG Test Reset: Reset for JTAG controller. Must be activated during
system reset or tied low during operation.
I
LSSD Test Mode Enable: The test enable pin is only used during
manufacturing test and must be low during operation. There is an
internal 13K Ω pull-down on this signal. Either leave this pin floating, or
connect it to a 10K Ω pull-down.
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