Rom / Peripheral Configuration Registers; Table 30. Device Attachment To Rom/Peripheral Bus - IBM CPC700 User Manual

Device Width
8-bit
16-bit
32-bit
64-bit
4.6.6 ROM / Peripheral Configuration Registers
The ROM / Peripheral configuration registers consist of one register per bank with each register being
used to configure the access modes and timings on a per-bank basis.
The CPC700 ROM controller has programmable timings that allow for ROM, SRAM, and peripheral sup-
port. An external READY input is provided to allow for device-paced transfers on both READs and
WRITEs. READY input, when enabled, may be configured to be synchronous or asynchronous.
Common register space is shared with the DRAM/SDRAM controller. A complete list of registers affecting
ROM operation follows.
Register
Symbol Register Name
RPB0P - ROM/Peripheral Bank Parameters
RPB4P
RBW ROM Bank Width
FWEN Flash ROM Write Enable
MCOPT1 Memory Controller Options 1
MEMTYPE Memory Type
MBEN Memory Bank Enable
MBSA0 - Memory Bank Starting Addresses
MBSA4
MBEA0 - Memory Bank Ending Addresses
MBEA4
RPB0P- ROM/Peripheral Access Parameters
RPB4P
Detailed descriptions of these registers can be found in Section 4.9, "Memory Controller Register Descrip-
tion".
4-32

Table 30. Device Attachment to ROM/Peripheral Bus

Table 31. ROM Configuration Registers
Data Bus Attachment
M_DATA[0:7]
M_DATA[0:15]
M_DATA[0:31]
M_DATA[0:63]
Memory Controller