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7.
Care must be exercised when the soft reset is used. This function is provided as a last means of
recovery when a failure in the IIC interface or IIC bus has occurred. The IIC interface will be com-
pletely cleared when the soft reset is activated. Any transmissions that might have been occurring
on the IIC bus will be immediately terminated without warning. Thus use of this function at an
improper moment could cause other IIC bus devices to hang.
8.
When multiple masters are used in a system, care must be taken to avoid certain situations that will
cause the IIC interface to either incorrectly monitor the state of the IIC bus or mishandle an arbitra-
tion. The situations that must be avoided are those which are listed in the Phillips Semiconductors
2
I
C Specification, dated 1995, Section 7.2. For your convenience, the section is summarized as fol-
lows:
If multiple masters can be simultaneously involved in a transfer to the same address, or device, then the
design of the system must be done in such a way that arbitration between:
-
A repeated START condition and a data bit does not occur.
-
A STOP condition and a data bit does not occur.
-
A repeated START condition and a STOP condition does not occur.
One example of a not allowed case would be if one master were to write one byte while another device
wrote two bytes to the same device. If this were to occur, the first master would issue a STOP while the
second master was sending the MSB of its second data byte.
9.
The soft reset bit in the extended control and slave status register should be set if the direct control
register is to be used.
CPC700 User's Manual—Preliminary
8-17
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