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6.1.2 UART Serial Clock
The serial clock provided to the CPC700 UARTs is equal to the PLL 0 input clock (SYS_CLOCK) divided
by four. If SYS_CLOCK is 33.33 MHz, an 8.33 MHz clock is provided to the UARTs for their serial clock
input. The serial clock can be further divided by programming the appropriate UART registers to produce
the desired baud rate for serial communications.
6.2 Internal Peripheral Power Management
The CPC700 internal peripherals, UARTs, IICs, and the General Purpose Timers (GPT), implement a form
of power management where clocks may be turned off to the their internal latches while the rest of the sys-
tem continues to operate around them. The CPR Peripheral Power Management Control Register can be
used for power management control. See Section 6.5.1, "Peripheral Power Management Control Register
(CPRPMCTRL)" for additional information.
Two types of power management are employed by the internal peripherals: absolute, and device paced.
With absolute power management, firmware requests that the peripheral place itself into sleep mode and it
sleeps immediately. With device paced power management, firmware requests a peripheral to sleep but
the peripheral may choose not to sleep until it is ready to switch to a sleep state. Furthermore, the periph-
eral may awaken on its own if needed and return to sleep as long as the firmware request for sleep mode
is still active. Likewise, firmware may wake the sleeping peripheral which will resume from sleep immedi-
ately.
The UARTs and the GPT both use absolute power management while the IICs use device paced.
6.3 Reset Control
The CPR manages reset to the CPC700. The sequence of events at power-on are as follows:
1.
System activates SYS_RESET_N (active low) to the CPC700.
2.
CPR holds reset active to the two internal PLLs for the entire time that SYS_RESET_N is active.
This ensures that all inputs and power levels are stable before removing reset to the PLLs.
3.
After SYS_RESET_N is deactivated, the PLL resets are deactivated and the PLL begins to lock. The
internal CPC700 reset signal remains active for 500us while the PLL is locking its frequency.
Strapping pins must be at valid logic levels prior to the de-assertion of SYS_RESET_N to allow PLL config-
uration bits to be set prior to the de-assertion of the reset to the PLLs. In addition, strapping pins must be
held until one input hold time after RESET_OUT_N has de-asserted. Typically the strapping pins are set
using external pullup or pulldown resistors if the CPC700 default values are not acceptable. Refer to Sec-
tion 6.4, "Power on Reset Pin Strapping Options", and Section 6.5.6, "Strapping Pin Register (CPRSTRA-
PREAD)" for additional information. Figure 44 illustrates the relationship between the SYS_RESET_N
input and the output signals RESET_OUT_N and RST_N along with minimum valid times for the strapping
pin inputs.
Output signals RESET_OUT_N and RST_N follow the internal reset signal (i.e. they are driven active for
500us following the de-assertion of SYS_RESET_N). In addition, they may be driven due to other condi-
tions:
• RESET_OUT_N will be driven for 500us following a write to the PLL tuning control register. This allows
time for the PLL to re-lock with it's new tuning bit values. Refer to Section 6.1.1, "PLL Tuning" and Sec-
tion 6.5.5, "PLL Tuning Control Register (CPRPLLTUNE)" for details.
• RST_N is intended to be used as the PCI reset when the CPC700 is the main system host bridge. In
addition to being activated during power-on reset, it may also be activated by writing to bit 12 of the
6-2
Clock, Power Management, and Reset
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