Pci Target Interface (Plb Master); Commands Generated As Plb Master - IBM CPC700 User Manual

The PTMs can be enabled/disabled by the Memory Access bit of the PCI Command Register. The address
ranges and sizes of the PTMs should be initialized before they are enabled. In the case where the PCI
interface is not the host bridge, the local CPU must initialize the PTM Size before enabling host configura-
tion (PCI interface Bridge Options 2 Register). This will ensure that the host experiences proper behavior
from the BAR registers.
See the Local Configuration Registers in Section 5.9.1.13 "PTM 1 Memory Size/Attribute" for details on
the PTM registers and see the PCI Configuration Registers in Section 5.9.3.12 "PCI Base Address Regis-
ter 1 (PCIPTM1BAR)" for details on the BAR registers.

5.6 PCI Target Interface (PLB Master)

This section describes how the CPC700 handles read and write requests from a PCI master device. The
CPC700 responds as a PCI target to PCI Memory transactions when the PCI address in within one of the
two PTM ranges and the Memory Access bit of the PCI Command Register is enabled. The CPC700
responds by claiming the PCI cycle, and mastering a cycle on the PLB.
Note: The CPC700 is also a PCI target for Configuration cycles when its IDSEL pin is active.
Note: The CPC700 will master abort if a configuration cycle is run to itself.

5.6.1 Commands Generated as PLB Master

The PCI interface generates PLB transactions based on the type and length of PCI transactions received.
The following sections describe the transaction types supported and outline the translation of commands
from one bus to the other.
The term "single-beat" in reference to PLB transfers refers to the M[x]_size=0000b transaction type. PCI
slave devices are referred to as "targets".
The PCI interface initiates the following commands as a PLB master:
•
1-4 Byte Read:
This command is generated in response to single beat or burst Memory Read commands from the
PCI bus.
•
Word Burst Read:
This command is generated in response to Memory Read Line and Memory Read Multiple com-
mands on the PCI bus.
•
1-4 Byte Write:
This command is generated in response to single beat (1-4 byte) Memory Write commands on the
PCI bus. This command is also generated when the PCI master uses non-contiguous byte enables
(see Section 5.6.2.6 "Byte Enable Handling" ). Single-beat Memory Write and Invalidate commands
are treated the same as single-beat Memory Writes.
•
Word Burst Write:
This command is generated in response to burst Memory Write and Memory Write and Invalidate
commands on the PCI bus.
Memory Write and Memory Write and Invalidate are treated identically with respect to the PLB. I.E. there is
nothing on the PLB that distinguishes a Memory Write from a Memory Write and Invalidate. Also, Memory
Read Line, and Memory Read Multiple are treated identically with respect to PLB commands.
The PCI interface does not generate line reads or line writes on the PLB.
5-8 PCI Interface