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clock
ALE
MA
READ#
WRITE#
RNW
CS#
OE#
R_DATA
READY
Figure 37. Burst Mode Read, Asynchronous Ready Enabled
4.7 ECC
The ECC module uses a 64 bit SEC/DED code which has been modified to support detection of single bit
address errors. The module supports a 64 data bit / 8 check bit interface, as well as a dual 32 data bit / 8
check bit interface (the dual 32-bit interface is used when the memory controller has an external 32 data bit
memory interface). Its features are described in Table 32.
Feature
Standard SEC/DEC coverage
Aligned nibble error detect
Single bit address error detect
32 bit or 64 bit mode
4-38
Table 32. ECC Features
Explanation
The ECC module corrects all single bit errors and detects
all double bit errors when reading from memory, including
the case where a single bit data and single bit address er-
ror occurs.
The ECC module detects any and all errors which may ex-
ist in an aligned four bit nibble.
If a (soft) single bit error occurred either on the write ad-
dress or the read address of a given memory transfer, the
ECC module will detect it and identify it as an address er-
ror.
The ECC module supports either 32 bits of data and 8
check bits, or 64 bits of data and 8 check bits
Memory Controller
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