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Chapter 3. Processor Interface
The processor interface is the portion of the CPC700 that attaches a PowerPC 60x or 7xx processor to the
internal PLB and the local memory controller. Through this interface, the processor may access the PCI
bus, local memory, and the CPC700's internal peripherals (UARTs, I
ler).
3.1 Features
Processor:
• PowerPC 603, 740, and 750 families
• 1 level processor address pipelining
• Support for processor "no-DRTRY" mode
• Processor Bus Arbiter (for Processor Interface core & snooping) w/ processor parking
• L1 cache coherency support
• 32 Byte Write Buffer to memory
• 32 Byte Write Buffer to PLB
• lwarx/stwcx. support (reservation cancelling snoops)
• Address Only cycle support
• Machine Check Interrupt request input (MCP_REQ) for processor error reporting
• Error tracking/status for processor transactions
PLB Interface
• PLB Master interface provides access to the PCI bus from the processor
• PLB Master interface provides access to internal peripherals from the processor
• PLB Slave interface provides access to the system memory from the PCI bus
Memory Interface
• Low latency access path to local memory
• Maintains coherency with the processor's L1 cache during PCI accesses to local memory.
3.2 Processor Interface Block Diagram
A detailed view of the function contained within the processor to PLB interface is shown in the block dia-
gram in Figure 3.
CPC700 User's Manual—Preliminary
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C ports, timers, and interrupt control-
3-1
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