Plb Error Status Register (Pesr); Figure 67. Plb Error Status Register (Pesr) - IBM CPC700 User Manual

12.2.3 PLB Error Status Register (PESR)

The read/clear PESR identifies timeout errors on PLB bus transfers, the master initiating the transfer,
and the type of transfer.
Each PESR[PTEn] field (n is the master ID) can be locked by the master. Once locked, PESR[PTEn]
fields cannot be updated if a subsequent error occurs until the corresponding PESR[FLCKn] field is
cleared. To clear a PESR field, write 1 to the field. Writing 0 to a PESR field does not affect the field.
PTE0 FLK0 FLK1
PTE1
0 1 2 3 4 5 6
R/W0
ALK0 R/W1 ALK1
0 PTE0 Master 0 PLB Timeout Error Status
0 No master 0 timeout error
1 Master 0 timeout error
1 R/W0 Master 0 Read/Write Status
0 Master 0 error operation was a write
1 Master 0 ICU error operation was a read
2 FLK0 Master 0 PESR Field Lock
0 Master 0 PESR field is unlocked
1 Master 0 field is locked
3 ALK0 Master 0 PEAR Address Lock
0 Master 0 PEAR is unlocked
1 Master 0 PEAR is locked
4 PTE1 Master 1 PLB Timeout Error Status
0 No master 1 timeout error
1 Master 1 timeout error
5 R/W1 Master 1 Read/Write Status
0 Master 1 error operation was a write
1 Master 1 error operation was a read
6 FLK1 Processor Core DCU PESR Field Lock
0 Master 1 PESR field is unlocked
1 Master 1 PESR field is locked
7 ALK1 Processor Core DCU PEAR Address Lock
0 Master 1 PEAR is unlocked
1 Master 1 PEAR is locked
8:31 Reserved
CPC700 User's Manual—Preliminary
7 8

Figure 67. PLB Error Status Register (PESR)

Master 0 is the 60x-PLB processor
interface.
Master 1 is the PCI interface.
31
12-3