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5.9.3.26 PCI Arbiter Control
Address offset: 47-44h
Width:
32
Reset Value:
00000000h
Access:
Read/Write
The CPC700 PCI arbiter provides arbitration for up to 6 devices at PCI speeds up to 33Mhz. It is enabled/
disabled based on the boot strapping of the CPC700 TT[4] signal. See Section 6.4 "Power on Reset Pin
Strapping Options" for more information.
The CPC700 PCI arbiter provides a single, fixed, balanced tree priority scheme as shown in Figure 42.
Input 0 of each individual block has priority over input 1 of the block. This means request 0 has the highest
priority while request 5 has the lowest. Bus parking modes and max transfer counts per grant can be pro-
grammed via the PCI Arbiter Control register.
.
Bit(s)
Name
26:0
Reserved
27
Bus Parking Mode
31:28
Max Transfer Count
Per Grant
5-36
Balanced Tree
Request
0
0
A0
1
1
2
0
A1
1
3
4
0
A2
5
1
Figure 42.Arbiter Priority Resolution
Table 53.PCI Arbiter Control Register Bits
Description
These bits are reserved and return 0 when read.
This bit controls the algorithm to use for determining the master on
which to park. 0=park on the CPC700, 1=park on last master.
These bits controls the maximum number of consecutive transac-
tions a master can perform while a pending lower priority request
exists.
0
B0
1
0
C0
1
B1
Grant
PCI Interface
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