Uicer - Uic Enable Register; Uiccr - Uic Critical Register; Figure 58. Uicer -- Uic Interrupt Enable Register; Figure 59. Uiccr -- Uic Critical Interrupt Register - IBM CPC700 User Manual

For the purposes of debug, a means of activating bits in the UICSR is necessary. A write to the UICSRS
will set bits in the UICSR when writing 1s to those bit positions. Note that setting an interrupt's status bit
while it's enabled in the UICER, will generate an external interrupt to the processor. Any location written
with a 0 will be unaffected. Reading this register will return the contents of the UICSR.
10.5.3 UICER — UIC Enable Register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MSB
The bits of the Configurable Interrupt Control Enable register correspond one to one with the bits of the
UICSR. Each bit in the UICER is used to enable or disable the reporting of the corresponding bit of the
UICSR. If an Enable register bit is set to 0, an interrupt captured in the corresponding bit of the UICSR will
not generate either an external or machine check interrupt signal to the processor. When the UICER bit is
a 1, an interrupt signal to the processor will occur if the UICSR bit is active. The type of generated signal
will be determined by the UICCR. The bits of the UICER register are written and read using the UICER
address.
10.5.4 UICCR — UIC Critical Register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MSB
The bits of the UICCR correspond one to one with the bits of the UICSR. Each bit in the UICCR is used to
determine whether an enabled interrupt, captured in the UICSR, will generate an external interrupt (INT) or
a machine check exception (MCP) to the processor. Interrupts that have their UICCR bit set to 1 will gener-
ate an INT, and those that have their UICCR bit set to 0 will generate an MCP. When properly enabled, INT
programmed interrupts will drive the CPC700's IRQ_OUT_N output signal to trigger an external interrupt to
the processor. MCP programmed interrupts, when properly enabled and when the MCP enable bit (bit 1) of
the PRIFOPT1 register is set, will drive the CPC700's MCP_N output signal to trigger a machine check
exception to the processor. The MCP enable bit of the PRIFOPT1 register must be set to enable MCP_N
output. See Section 3.16.1, "PRIFOPT1 - Processor Interface Options 1" for more information.
10-6
Interrupt [0] Enable
Interrupt [1] Enable
Interrupt [2] Enable
Interrupt [3] Enable
Interrupt [4] Enable
• • •
• • •

Figure 58. UICER -- UIC Interrupt Enable Register

Interrupt [0]
Interrupt [1]
Interrupt [2]
Interrupt [3]
Interrupt [4]
• • •
• • •

Figure 59. UICCR -- UIC Critical Interrupt Register

Interrupt [31] Enable
• • •
LSB
Interrupt [31]
• • •
LSB
Interrupt Controller