Table 63. Pci Frequency Modes - IBM CPC700 User Manual

Table 62. General Strapping Options (Continued)
Function Notes
System PLL
Shared DQM / ECC Enable DQM [1:7]
Enable ECC [1:7]
Note: Boot ROM Bank Width 0 and 1 correspond to the ROM Bank Width register bits 0 and 1 respectively.
See Section 4.9.3.2, "RBW - ROM Bank Width".
Clocking Mode
Async
Async
Async
Sync (2:1)
The status of the pin strapping may be read through the register shown in Table 69..
CPC700 User's Manual—Preliminary
CPC700 I/O
TT[0]
Enable PLL
Bypass PLL

Table 63. PCI Frequency Modes

PCI Frequency Range
25 - 35 MHz
34 - 50 MHz
49 - 67 MHz
25 - 35 MHz
TT[1] TT[4]
CPC700 I/O
TSIZ(1) TSIZ(2)
pulldown don't care
pulldown pulldown
pulldown
pullup don't care
TSIZ[0] GBL_N
pulldown
pullup
pullup
pulldown
PCI_66_STR
AP
pulldown
pullup
pullup pullup
pulldown
6-5