Cpr Registers; Peripheral Power Management Control Register (Cprpmctrl); Peripheral Reset Control Register (Cprreset); Table 64. Power Management Control Register - IBM CPC700 User Manual

6.5 CPR Registers

6.5.1 Peripheral Power Management Control Register
(CPRPMCTRL)
Address: FF50_0900h
Width: 32 bits
Reset Value: 0000_0000
Access: Read/Write
This register provides power management control for the CPC700's UART, IIC, and GPT internal peripher-
als. Note that a peripheral will remain in sleep mode as long as its sleep bit is set in the CPRPMCTRL reg-
ister. The peripheral's sleep bit must be cleared (written to logic 0) to enable the peripheral.

Table 64. Power Management Control Register

Bit Name
0 UART0_SLEEP
1 UART1_SLEEP
2 IIC0_SLP_INIT
3 IIC1_SLP_INIT
4 GPT_SLEEP
5:31

6.5.2 Peripheral Reset Control Register (CPRRESET)

Address: FF50_0904h
Width: 32 bits
Reset Value: 0000_0000
Access: Read/Write
This register can be used to reset the CPC700's UART, IIC, and GPT internal peripherals. Note that setting
a peripheral's reset bit in the CPRRESET register will hold the peripheral in a reset state until its reset bit is
cleared (written to a logic 0).
6-6
Default Description
0 UART 0 Sleep
0 - Enable UART 0
1 - Force UART 0 to Sleep
0 UART 1 Sleep
0 - Enable UART 1
1 - Force UART 1 to Sleep
0 IIC 0 Sleep Init
0 - IIC 0 Sleep mode disabled
1 - IIC 0 Sleep mode requested
This bit indicates to the IIC core that it may go to sleep when it is ready to.
0 IIC 1 Sleep Init
0 - IIC 0 Sleep mode disabled
1 - IIC 0 Sleep mode requested
This bit indicates to the IIC core that it may go to sleep when it is ready to.
0 General Purpose Timer Sleep
0 - Enable GPT
1 - Force GPT to Sleep
0 Reserved - Read returns 0
Clock, Power Management, and Reset