Rbw - Rom Bank Width - IBM CPC700 User Manual

Memory controller and pci bridge
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4.9.3.2 RBW - ROM Bank Width

Address Offset:
x88
Width:
32
Reset Value:
x0000_0000
Access:
Read/Write
This register must be configured to indicate the width of the installed ROM or external peripheral in each
bank.
Bit
Name
0:1
64N8_0
2:3
64N8_1
4:5
64N8_2
6:7
64N8_3
8:9
64N8_4
10:31
4-54
Reset
Description
Value
0*
ROM Bank 0 width.
00 - 8 bit
01 - 16 bit
10 - 32 bit
11 - 64 bit
*Reset value determined by strapping option. See Section 6.4,
"Power on Reset Pin Strapping Options".
Strapping Pins
Bit 0 - TT(0) (Processor bus Transfer Type)
Bit 1 - TT(1)
0
ROM Bank 1 width.
00 - 8 bit
01 - 16 bit
10 - 32 bit
11 - 64 bit
0
ROM Bank 2 width.
00 - 8 bit
01 - 16 bit
10 - 32 bit
11 - 64 bit
0
ROM Bank 3 width.
00 - 8 bit
01 - 16 bit
10 - 32 bit
11 - 64 bit
0
ROM Bank 4 width.
00 - 8 bit
01 - 16 bit
10 - 32 bit
11 - 64 bit
0s
Reserved
Memory Controller

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