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6.5.6 Strapping Pin Register (CPRSTRAPREAD)
Address:
FF50_0914h
Width:
32 bits
Reset Value:
Depends on strapping pins
Access:
Read Only
The default values shown indicate the default values if no external strapping resistors are applied. Refer to
Section 6.4, "Power on Reset Pin Strapping Options" for details.
Status of the pin strapping may be read through the registers shown in Table 69.
Bit
Name
0
PCIFREQ0
(Pin TSIZ[2])
1
PCIFREQ1
(Pin PCI_66_STRAP)
2
MUXARBPAR
(Pin TT[4])
3
PLL0BYPASS
(Pin TSIZ[0])
4
SYNCASYNC
(Pin TSIZ[1])
5
DQMNECC
(Pin GBL_N)
6:31
CPC700 User's Manual—Preliminary
Table 69. Strapping Pin Register
Default
Description
0
PCI Frequency Select 0
In Asynchronous PCI Mode
0 - PCI Frequency < 50MHz
1 - PCI Frequency > 50MHz
In Synchronous PCI Mode - This bit is a "Don't Care"
0
PCI Frequency Select 1
0 - PCI Frequency = 25 - 35MHz
1 - PCI Frequency = 34 - 67MHz
0
PCI Arbiter / Processor Data Parity Mux Control
0 - Enable Processor Data Parity (PCI Arbiter Disabled)
1 - Enable Internal Arbiter (Parity bus becomes arbiter I/O)
0
System Clock PLL Bypass
0 - Enable PLL
1 - Bypass PLL
0
Sync vs. Async Select (PCI PLL Bypass)
0 - Enable Asynchronous PCI Mode
1 - Enable Synchronous PCI Mode
0
Select either DQM[1:7] or ECC[1:7] to be muxed on ECC/DQM lines
0 - ECC[1:7]
1 - DQM[1:7]
0
Reserved - Reads return 0
6-9
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