Capture Timers; Capture Timers Interrupt; Figure 48. Capture Timers Logic/Block Diagram - IBM CPC700 User Manual

9.2.2 Capture Timers

Each of the five capture timers (GPTCAPT0-4) is 32 bits wide and captures the TBC value whenever a
capture event is generated via the GPT Capture Event Generation register (CPRCAPTEVNT) and the cor-
responding enable bit is set (1) in the GPT Capture Enable (GPTCE) register. If the corresponding GPT
Interrupt Mask (GPTIM) bit is disabled (0), the event's interrupt status bit will be set in the GPT Interrupt
Status (GPTIS) register. Further, if the corresponding GPT Interrupt Enable (GPTIE) register bit is set (1),
the interrupt will be sent to the CPC700 interrupt controller. If enabled in the CPC700 interrupt controller,
the capture event can be used to interrupt the processor. See Figure 48 for the Capture Timers Logic/Block
Diagram.
Capture
Event
(1/5)
(CPRCAPTEVNT)
Capture Enable (GPTCE)
Interrupt Mask (GPTIM)
Interrupt Enable (GPTIE)
Note that the CPRCAPTEVNT register is implemented in the Clock, Power Management, and Reset (CPR)
logic of the CPC700. The bits in the CPRCAPTEVNT register can be made falling-edge active (set to 0 to
trigger) or rising-edge active (set to 1 to trigger) via the GPT Edge Detection Control (GPTEC) register.
Refer to Section 6.5.3, "GPT Capture Event Generation Register (CPRCAPTEVNT)" for details.

9.2.2.1 Capture Timers Interrupt

The following steps must happen for a capture timer interrupt to occur:
• If needed, the corresponding bit should be programmed in the GPTSC register to determine if the GPT
capture events in the CPRCAPTEVNT register are synchronized to the TBC clock source.
• If needed, the corresponding bit should be programmed in the GPTEC register to determine if the GPT
capture events in the CPRCAPTEVNT register are rising-edge or falling-edge active.
• The corresponding enable bit must be set (1) in the GPT Capture Enable (GPTCE) Register.
CPC700 User's Manual—Preliminary
TBCclk
Sync
Sel
Sync Control (GPTSC)

Figure 48. Capture Timers Logic/Block Diagram

Rise
Detect
Fall
Detect
Sel
Edge Control (GPTEC)
Time Base Counter (TBC)
Capture
Valid (1/5)
Capture Register (CAPTx)
Interrupt Status (GPTIS)
Capture Int.
(1/5) to
Int. Controller
9-3