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extended control and slave status register when the first interrupt occurred. Then, sometime later, the rou-
tine wishes to clear this status by writing 0x10 back to the register. If the slave write operation completes in
between the time the register is read and written, the register will contain a 0x30 when the 0x10 is written.
Since writing a bit to logic 0 has no effect once it is logic 1, the slave write complete status is not lost. Note
that if bits were cleared by writing a logic 0, then status would have been lost.
The IIC interface will merge slave read (write) needs service and slave read (write) complete interrupts into
one interrupt under certain conditions. If a slave read (write) needs service interrupt is active, or queued,
and a slave read (write) complete interrupt occurs, and the extended control and slave status register has
not been read yet, then the two interrupts are merged into a single interrupt. This merge function is auto-
matically done in the IIC interface's logic and is not under the program's control.
8.6 General Considerations
1.
After a reset, the IIC interface enters the unknown IIC bus state. This state will be exited when either
activity is seen on the bus or when the exit unknown IIC bus state bit, in the mode control register, is
set to a logic 1. If the IIC interface is being used in a single master system as the master, then the
exit unknown IIC bus state bit must be used to force the logic out of the unknown state.
2.
Once a byte is written into either the master or slave buffer, a total of four clock periods must occur
before the data can be read. Flushing the master or slave buffer also needs four clock periods to
complete.
3.
The master and slave buffers are actually 4 by 1 byte-wide FIFOs. Thus the last byte written into a
buffer is not the first one read out. Care must be exercised by the program when these buffers are
written or read. As an example, consider the case where the program wants to send one byte of
data out over the IIC interface. One of the first things that should be done by the program is to write
the byte that is to be sent into the buffer. If the program wanted to check that the byte is actually
inside the buffer, it could be assumed that the program could perform a read of the buffer. If this were
done, then the program actually would be removing the byte that was just put into the buffer. If the
program were to then execute the transfer, invalid data would be sent out over the IIC interface
because the buffer is now empty.
4.
Care must be used if the IIC device driver program intends to service slave/master operations by
reacting to the "slave data buffer has data" bit (bit 4) in the extended control and slave status regis-
ter, or to the "master data buffer has data" bit (bit 2) in the status register. These bits go active when-
ever the buffer has data in any of its stages. Consider the case where the master buffer is empty and
gets loaded with a byte received via the IIC bus. In this case, the byte goes into stage 4 and the
"master data buffer has data" status bit goes active to a logic 1. At this point in time, stages 1, 2, and
3 have no data in them. If the program were to read data at this point, it would read invalid data
because reads from the buffer actually read from state 1 and there is no data in stage 1 yet. Valid
data will not appear in stage 1 until four clock periods after the "master data buffer has data" status
bit went active. This latency must be fully understood if the program intends to read data from the
buffer as soon as it has arrived.
5.
The recommended order for responding to the slave needs service request is to first read (write)
data out of (into) the slave buffer, then clear the needs service or done status bit or bits, and finally,
clear the IRQ.
6.
There is no timeout function implemented in the IIC interface. Thus, there is no timeout during data
transfers. If this type of error recovery function is needed, it must be implemented in another part of
the system. The IIC interface's halt operation, along with reset, can be used by the system designer
to implement any desired error recovery.
8-16
IIC
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