Pci Interface Address Maps; Plb Address Map - IBM CPC700 User Manual

Table 40.PCI Interface Configuration Register Offsets (Continued)
PCI Config Register
PCICACHELS
PCILATTIM
PCIHDTYPE
PCIBIST
PCIBAR0
PCIPTM1BAR
PCIPTM2BAR
Reserved
Reserved
PCISUBSYSID
PCISUBSYSVENDID
Reserved
PCIINTLN
PCIINTPN
PCIMINGNT
PCIMAXLTNCY
PCIBUSNUM
PCISUBBUSNUM
PCIDSCCNT
PCIARBCNTL
PCIERREN
PCIERRSTS
PCIBRDGOPT1
SESR
SEAR0
SEAR1
Reserved
Reserved
PCIBRDGOPT2

5.5 PCI Interface Address Maps

The PCI interface supports a flexible, programmable address map.

5.5.1 PLB Address Map

The PCI interface responds as a target on the PLB bus in several address ranges. These ranges allow the
processor (a PLB master) to configure the PCI interface, and to cause the PCI interface to generate Mem-
ory, I/O, Config, Interrupt Acknowledge, and Special cycles on the PCI bus. Table 41. shows the address
map from the view of the PLB (i.e., as decoded by the PCI interface as a PLB slave).
5-4
Offset R/W Description
0C R Cache Line Size
0D R/W Latency Timer
0E R Header Type
0F R Built In Self Test Control
10 R Unused BAR 0
14 R/W PTM 1 BAR
18 R/W PTM 2 BAR
1C - 27 Unused BARs
28 - 2B Unused Cardbus
2C R/W PCI Subsystem ID
2E R/W PCI Subsystem Vendor ID
30 - 3B Unused or Reserved
3C R/W Interrupt Line
3D R Interrupt Pin
3E R Minimum Grant
3F R Maximum Latency
40 R Bus Number
41 R Subordinate Bus Number
42 R Disconnect Counter
47 - 44 R/W PCI Arbiter Control
48 R/W Error Enable
49 R/W Error Status
4B - 4A R/W Bridge Options 1
4F - 4C R/W PLB Slave Error Syndrome Register
53 - 50 R PLB Slave Error Address Register 0
57 - 54 R PLB Slave Error Address Register 1
5B - 58
5F - 5C
61 - 60 R/W Bridge Options 2
PCI Interface