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5.8 Other Bridge Functions
5.8.1 Collision Resolution
The PCI interface must resolve collisions when both a PLB master and a PCI master attempt accesses
through the PCI interface at the same time. summarizes how these collisions are resolved. In general,
PLB postable writes are always accepted (buffer space allowing), and passed to the PCI when given the
chance. PCI master writes are always accepted (buffer space allowing), but cause PLB reads and non-
postable writes to be rearbitrated to clear the path to the PLB. PLB reads and non-postable writes proceed
as long as there is no PCI master activity (which causes the PLB cycle to be rearbitrated). PCI master
reads are always allowed to proceed, and cause PLB reads and non-postable writes to be rearbitrated.
Internal configuration accesses have their own set of rules. Configuration writes are not allowed to com-
plete while any write data is posted in the bridge or while the PCI Master is prefetching. Otherwise, they
have no restrictions. Configuration reads have no restrictions at all.
PCI write to PLB
PCI read from
PLB
5.8.2 Completion Ordering
The CPC700 implements the following completion ordering rules:
1.
PCI master writes are accepted if there is room in the PCI write post buffer.
2.
New PCI master reads are accepted if there is no delayed read (DRR or DRC) in progress:
a.
If PCI write post buffer is empty, then begin a connected tenure read, resulting in:
1)
Read completes connectedly.
2)
Initial target latency timer gets critical, so turn into a delayed read (enter DRR state).
b.
If PCI write post buffer is not empty, then begin delayed read (enter DRR state).
Delayed reads are handled as follows:
1)
While in DRR state, retry all PCI master reads. Wait for all PCI master writes that were
posted before entering DRR state to complete on PLB.
2)
Execute PLB read, enter DRC state.
3)
While in DRC state, retry all PCI master reads if the address/control does not match. If
it does match, pass the read data to the PCI master. If data is passed, exit the DRC
state.
3.
PLB master writes are accepted if there is room in the PLB write post buffer.
CPC700 User's Manual—Preliminary
Table 45.Collision Resolution
PLB Read from PCI
Rearb PLB master
(reads flush writes)
Rearb PLB master
PLB Postable Write to
PCI
no conflict
No conflict
PLB non-postable Write
to PCI
Rearb PLB master
Rearb PLB master
5-17
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