Plb Arbiter Registers; Plb Arbiter Control Register (Pacr); Plb Error Address Register (Pear); Figure 65. Plb Arbiter Control Register (Pacr) - IBM CPC700 User Manual

12.2 PLB Arbiter Registers

PLB arbiter registers are accessed using the addresses in Table 102.
Mnemonic
PACR
PEAR
PESR

12.2.1 PLB Arbiter Control Register (PACR)

The PACR controls PLB arbitration priority, which is determined by PLB priority mode and PLB priority
order.
PPM
0 1 2 3
PPO
0 PPM PLB Priority Mode
0 Fixed
1 Fair
1:2 PPO PLB Priority Order
00 Masters 0, 1
01 Masters 1, 0
10 Reserved
11 Reserved
3:31 Reserved

12.2.2 PLB Error Address Register (PEAR)

The read-only PEAR contains the address of the access on which a bus timeout error occurred.
The PEAR can be locked by the master. Once locked, the PEAR cannot be updated, if a subsequent
error occurs, until all PESR[FLCKn] fields are cleared (n is the master ID).
0
0:31 Address of bus timeout error
12-2
Table 102. PLB Arbiter Registers
Register Name
PLB Arbiter Control Register
PLB Error Address Register
PLB Error Status Register

Figure 65. PLB Arbiter Control Register (PACR)

Figure 66. PLB Error Address Register (PEAR)

Address Access
0xFF50_085C R/W
0xFF50_0858 R/O
0xFF50_0850 R/Clear
Processor Local Bus (PLB)
31
31