IBM CPC700 User Manual page 12

Figures
Figure 46. 7-Bit Addressing 8-1
Figure 47. 10-Bit Addressing 8-2
Figure 48. Capture Timers Logic/Block Diagram 9-3
Figure 49. Compare Timer Logic/Block Diagram 9-4
Figure 50. Capture Timers Enable Register 9-6
Figure 51. Capture Events Edge Detection Control Register 9-7
Figure 52. Capture Events Synchronization Control Register 9-7
Figure 53. Interrupt Mask Register 9-8
Figure 54. Interrupt Status Register 9-8
Figure 55. Interrupt Enable Register 9-9
Figure 56. UICSR -- UIC Status Register 10-5
Figure 57. UICSRS -- UIC Status Register -- Set 10-5
Figure 58. UICER -- UIC Interrupt Enable Register 10-6
Figure 59. UICCR -- UIC Critical Interrupt Register 10-6
Figure 60. UICPR - UIC Polarity Register 10-7
Figure 61. UICTR -- UIC Trigger Register 10-7
Figure 62. UICMSR -- UIC Masked Status Register 10-8
Figure 63. UICVCR -- IUC Vector Configuration Register 10-8
Figure 64. UICVR -- UIC Vector Register 10-9
Figure 65. PLB Arbiter Control Register (PACR) 12-2
Figure 66. PLB Error Address Register (PEAR) 12-2
Figure 67. PLB Error Status Register (PESR) 12-3
Figure 68. Bridge Error Address Register (GEAR) 13-1
Figure 69. OPB Bridge Error Status Register (GESR) 13-1
xii List of Figures