IBM CPC700 User Manual page 14

Tables
Table 47. PMM 0 Mask/Attribute Register Bits 5-21
Table 48. PTM 1 Size/Attribute Register Bits 5-24
Table 49. PTM 2 Size/Attribute Register Bits 5-25
Table 50. PCI Command Register Bits 5-28
Table 51. PCI Status Register Bits 5-29
Table 52. PCI BAR 1 5-32
Table 53. PCI Arbiter Control Register Bits 5-36
Table 54. Error Enable Register Bits 5-37
Table 55. Error Status Resister Bits 5-38
Table 56. Bridge Options Register Bits 5-39
Table 57. Slave Error Syndrome Register Bits 5-40
Table 58. Bridge Options 2 Register Bits 5-42
Table 59. Register Settings 5-43
Table 60. PLB Unsupported Transfer Types 5-44
Table 61. PLL Usage 6-1
Table 62. General Strapping Options 6-4
Table 63. PCI Frequency Modes 6-5
Table 64. Power Management Control Register 6-6
Table 65. Peripheral Reset Control Register 6-7
Table 66. GPT Event Generation Register 6-7
Table 67. PLL Configuration Access Register 6-8
Table 68. PLL Tuning Control Register 6-8
Table 69. Strapping Pin Register 6-9
Table 70. UART Core Configuration Registers 7-3
Table 71. Summary of UART Registers (Big Endian Notation) 7-4
Table 72. Line Control Register Description 7-5
Table 73. Line Status Register Description 7-6
Table 74. FIFO Control Register Description 7-7
Table 75. Interrupt Identification Register Description 7-8
Table 76. Interrupt Enable Register Description 7-9
Table 77. UART Divisor Latch Settings for Certain Baud Rates 7-10
Table 78. IIC Registers 8-2
Table 79. Master Data Buffer 8-4
Table 80. Master Data Buffer 8-4
Table 81. Lo Master Address Register 8-5
Table 82. Hi Master Address Register 8-5
Table 83. Control Register 8-6
Table 84. IIC Response to Control Settings 8-6
Table 85. Mode Control Register 8-7
Table 86. Status Register 8-8
Table 87. Extended Status Register 8-10
Table 88. Lo Slave Address Register 8-10
Table 89. Hi Slave Address Register 8-11
Table 90. Clock Divide Register 8-11
Table 91. IIC Clock Divide Programming 8-12
Table 92. Interrupt Mask Register 8-12
xiv List of Tables