Uicsr - Uic Status Register; Uicsrs - Uic Status Register - Set; Figure 56. Uicsr -- Uic Status Register - IBM CPC700 User Manual

Register
UICSR
UICSRS
UICER
UICCR
UICPR
UICTR
UICMSR
UICVR
UICVCR
10.5.1 UICSR — UIC Status Register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MSB
The Configurable Interrupt Control Status register is where all internal and external interrupts are captured
and held until the bits are intentionally reset. The only way to reset the bits in this register is to write to this
register, using the Read/Clear address and a data value of 1 in every bit that is to be reset. It may be read
using the same address.
The normal hardware setting of bits in this register is not affected by the values of any other UIC register
and should only occur in the case of an interrupt signal of the type designated in the configuration.
10.5.2 UICSRS — UIC Status Register – Set
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
MSB
CPC700 User's Manual—Preliminary
Table 99. UIC Core Configuration Registers
Address R/W
FF50_0880 R/C
FF50_0884 R/S
FF50_0888 R/W
FF50_088C R/W
FF50_0890 R/W
FF50_0894 R/W
FF50_0898 R
FF50_089C R
FF50_08A0 W
Interrupt [0] Status
Interrupt [1] Status
Interrupt [2] Status
Interrupt [3] Status
Interrupt [4] Status
• • •
• • •

Figure 56. UICSR -- UIC Status Register

Interrupt [0] Set
Interrupt [1] Set
Interrupt [2] Set
Interrupt [3] Set
Interrupt [4] Set
• • •
• • •
Figure 57. UICSRS -- UIC Status Register -- Set
Description
UIC Status Register (Read/Clear)
UIC Status Register (Set)
UIC Enable Register
UIC Critical Register
UIC Polarity Register
UIC Trigger Register
UIC Masked Status Register
UIC Vector Register
UIC Vector Configuration Register
Interrupt [31] Status
• • •
LSB
Interrupt [31] Set
• • •
LSB
10-5