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5.4 PCI Interface Registers
The PCI Interface registers listed in Table 39., reside at memory mapped addresses in PLB space. See
Section 5.9.1 "PCI Interface Local Configuration Register Descriptions" for additional information.
Register
PMM0LA
PMM0MA
PMM0PCILA
PMM0PCIHA
PMM1LA
PMM1MA
PMM1PCILA
PMM1PCIHA
PMM2LA
PMM2MA
PMM2PCILA
PMM2PCIHA
PTM1MS
PTM1LA
PTM2MS
PTM2LA
PCICFGADR
PCICFGDATA
The PCI Interface configuration registers listed in Table 40., are accessed through an indirect method
employing an address register, PCICFGADR, and a data register, PCICFGDATA. To access one of the PCI
Interface configuration registers, write the appropriate index to register PCICFGADR, then read the data
from or write the data to register PCICFGDATA. See Section 5.9 "Bridge Configuration" for important infor-
mation regarding these registers.
PCI Config Register
PCIVENDID
PCIDEVID
PCICMD
PCISTATUS
PCIREVID
PCIINTCLS
PCISUBCLS
PCIBASECC
CPC700 User's Manual—Preliminary
Table 39.PCI Interface Local Configuration Registers
Address
R/W
FF40_0000
R/W
FF40_0004
R/W
FF40_0008
R/W
FF40_000C
R/W
FF40_0010
R/W
FF40_0014
R/W
FF40_0018
R/W
FF40_001C
R/W
FF40_0020
R/W
FF40_0024
R/W
FF40_0028
R/W
FF40_002C
R/W
FF40_0030
R/W
FF40_0034
R/W
FF40_0038
R/W
FF40_003C
R/W
FEC0_0000
R/W
FEC0_0004
R/W
Table 40.PCI Interface Configuration Register Offsets
Offset
R/W
01 - 00
R/W
03 - 02
R
05 - 04
R/W
07 -06
R/W
08
R
09
R/W
0A
R/W
0B
R/W
Description
PMM 0 Local Address
PMM 0 Mask/Attribute
PMM 0 PCI Low Address
PMM 0 PCI High Address
PMM 1 Local Address
PMM 1 Mask/Attribute
PMM 1 PCI Low Address
PMM 1 PCI High Address
PMM 2 Local Address
PMM 2 Mask/Attribute
PMM 2 PCI Low Address
PMM 2 PCI High Address
PTM 1 Memory Size
PTM 1 Local Address
PTM2 Memory Size
PTM2 Local Address
PCI Configuration Address Register
PCI Configuration Data Register
Description
Vendor ID
Device ID
Command Register
Status Register
Revision ID
Interface Class
Sub-Class Code
Base Class Code
5-3
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