Chapter 13. Opb Bridge; Opb Bridge Error Address Register (Gear); Opb Bridge Error Status Register (Gesr); Figure 68. Bridge Error Address Register (Gear) - IBM CPC700 User Manual

Chapter 13. OPB Bridge

The On-Chip Peripheral (OPB) Bridge provides a PLB Master with control of the OPB bus and access
to OPB peripherals. The PLB to OPB bridge registers are accessed using the addresses in
Table 103.
Mnemonic
GEAR
GESR

13.1 OPB Bridge Error Address Register (GEAR)

The read-only GEAR reports the address of a PLB to OPB transfer that results in an error. The PLB to
OPB bridge writes the error address in the GEAR, unless the associated GESR[ALCKn] field is set
(master ID specified by n). Once locked, the PLB to OPB bridge cannot write GEAR until all
GESR[ALCKn] fields that are set are cleared.
0
0:31 Address of bus error

13.2 OPB Bridge Error Status Register (GESR)

The PLB to OPB bridge writes error information into the GESR.
GESR fields can be locked using the GESR[FLKn] and GESR[ALKn] fields (n is the master ID). Once
locked, the GESR fields associated with a master cannot be overwritten if a subsequent error occurs
until the locking fields are cleared. To clear a lock, write 1 to the GESR[FLKn] and GESR[ALKn] fields
that are set. Writing 0 to a lock field does not affect the field.
PTE0 FLK0 PTE1
0 1 2 3 4 5 6 7 8 9 10
R/W0 ALK0 R/W1 ALK1
0:1 PTE0 PLB Timeout Error Status Master 0
00 No master 0 error occurred
01 Master 0 timeout error occurred
10 Master 0 slave error occurred
11 Reserved
CPC700 User's Manual—Preliminary

Table 103. OPB Bridge Registers

Register Name
Bridge Error Address Register
Bridge Error Status Register

Figure 68. Bridge Error Address Register (GEAR)

FLK1

Figure 69. OPB Bridge Error Status Register (GESR)

Address
0xFF50_0818
0xFF50_0810
Master 0 is the 60x-PLB processor
interface.
Access
R/O
R/Clear
31
31
13-1