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2.3 Memory Interface Signals
Active
Signal Name
Level
M_DATA[0:63]
High
ECC[0]
High
DQM[0]
High
ECC/DQM[1:7]
High
MA[12:0]
High
BANK_SEL_N
Low
[0:4]
WE_N
Low
CKE
High
RAS_N
Low
CAS_N
Low
BA[1:0]
High
ROM_OE_N
Low
ROM_WE_N
Low
ROM_RD_N
Low
ROM_WR_N
Low
ROM_RNW
High
CPC700 User's Manual—Preliminary
I/O
Description
I/
Memory Data: 64-bit memory data bus. If configured for a 32-bit memory
O
interface, M_DATA[0:31] are used.
I/
Error Correction Code Data[0]: Bit [0] of the 8-bit Error correction code
O
data bus. Bits [1:7] are multiplexed with the DQM bus bits [1:7]. If ECC is
enabled a single DQM (bit 0) is connected to all DQM inputs on all DIMMs.
O
SDRAM Data Mask[0]: Data byte mask bus bit 0. This bit is connected to all
DQM inputs of all DIMMs if ECC is used in the system. If ECC is not used,
then ECC/DQM[1:7] lines make up the remainder of the 8-bit DQM bus.
DQM[0] corresponds to Memory Data Lane 0. During reads, the CPC700
asserts DQM high to cause the SDRAM to tristate the SDRAM output. If
DQM is low, the SDRAM drives the data onto the output.
During writes, DQM high commands the SDRAM to mask the data. The input
data is ignored and the previous contents of the SDRAM are retained. When
DQM is low during a write, the SDRAM data is updated as usual.
I/
ECC[1:7] / DQM[1:7]: Multiplexed ECC and DQM bit [1:7]. The use of either
O
ECC or the additional DQM lines are governed by a pin strapping option.
DQM7 corresponds to Memory Data Lane 7
O
Memory Address[12:0]: Memory address bus. Memory address bit 10 also
functions as the auto-precharge bit. Signal range is in little endian notation.
O
Memory Bank Select[0:4]: Five Banks are supported with bank 0 required
to contain the boot ROM device. The remaining 4 banks may be programmed
for SDRAM, ROM/Flash, SRAM, or peripheral devices.
O
Write Enable: SDRAM Write Enable.
O
Clock Enable: SDRAM Clock Enable.
O
Row Address Strobe: SDRAM Row Address Strobe.
O
Column Address Strobe: SDRAM Column Address Strobe.
O
Bank Address[1:0]: SDRAM Bank Address. The Bank Address accesses
one of up to 4 internal banks within an SDRAM chip. Signal range is in little
endian notation.
O
ROM Output Enable: Output enable for ROM / Peripheral devices.
O
ROM Write Enable: Write enable for ROM / Peripheral devices.
O
ROM Read: Read signal for ROM / Peripheral devices.
O
ROM Write: Write signal for ROM / Peripheral devices.
O
ROM Read-Not-Write: The ROM_RNW signal may be used as a direction
indicator for external data bus transceivers in the event that the system
designer chooses to isolate the ROM / Peripheral bus from the SDRAM data
bus.
2-5
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