IBM CPC700 User Manual

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CPC700

Memory Controller and PCI Bridge

User's Manual

Version 1.1

Issue Date: 3/22/00

Preliminary

Table of Contents

Summary of Contents for IBM CPC700

Page 1 CPC700 Memory Controller and PCI Bridge User’s Manual Version 1.1 Issue Date: 3/22/00 Preliminary...
Page 2 Nothing in this document shall operate as an express or implied license or indemnity under the intellectual property rights of IBM or third parties. The products described in this document are not intended for use in implantation or other direct life-support applications where malfunction may result in physical harm or injury to persons.
Page 3: Table Of Contents
3.12 PLB Slave Interface to Memory (PCI to Memory) .......3-17 3.13 CPC700 Response for PCI to Memory Accesses .......3-18 3.14 Processor to DCR/Conﬁguration Space .
Page 4: Table Of Contents
Table of Contents 3.16.2 ERRDET1 - Error Detection 1 ........3-26 3.16.3 ERREN1 - Error Detection Enable 1 .
Page 5 5.8.2 Completion Ordering ..........5-17 CPC700 User’s Manual—Preliminary...
Page 6 Table of Contents 5.8.2.1 PCI Producer-Consumer Model ........5-18 5.8.3 PCI Frequency Options .
Page 7 6.1 CPC700 Clock Control........
Page 8 Table of Contents 7.3 FIFO Operation ............7-11 7.3.1 Interrupt Mode .
Page 9 14.1 CPC700 Registers........
Page 10 Table of Contents Table of Contents...
Page 11: Figures
Figure 40. Big-Endian 5-20 Figure 41. Format of PCICFGADR Register 5-26 Figure 42. Arbiter Priority Resolution 5-36 Figure 43. Example Address Map 5-49 Figure 44. CPC700 Reset and Strapping Pin Timing 6-3 Figure 45. Typical Reset System 6-3 CPC700 User’s Manual—Preliminary...
Page 12 Figures Figure 46. 7-Bit Addressing 8-1 Figure 47. 10-Bit Addressing 8-2 Figure 48. Capture Timers Logic/Block Diagram 9-3 Figure 49. Compare Timer Logic/Block Diagram 9-4 Figure 50. Capture Timers Enable Register 9-6 Figure 51. Capture Events Edge Detection Control Register 9-7 Figure 52.
Page 13 Table 6. CPC700 Address Map - PCI View 3-4 Table 7. Supported Processor Transfer Type Encodings/Response 3-5 Table 8. CPC700 Response for processor to System Memory Transactions 3-7 Table 9. Processor to Memory Cycle Translation 3-7 Table 10. PLB Master Cycles 3-8 Table 11.
Page 14 Tables Table 47. PMM 0 Mask/Attribute Register Bits 5-21 Table 48. PTM 1 Size/Attribute Register Bits 5-24 Table 49. PTM 2 Size/Attribute Register Bits 5-25 Table 50. PCI Command Register Bits 5-28 Table 51. PCI Status Register Bits 5-29 Table 52. PCI BAR 1 5-32 Table 53.
Page 15 Table 97. GPT Registers Reset Values 9-5 Table 98. Interrupt Assignments 10-3 Table 99. UIC Core Configuration Registers 10-5 Table 100. CPC700 PLB Master Assignments 12-1 Table 101. Registers Controlling PLB Master Priority Assignments 12-1 Table 102. PLB Arbiter Registers 12-2 Table 103.
Page 16 Tables List of Tables...
Page 17: Chapter 1. Introduction
• Byte swapping supported for bi-endian operation. With versions that support processor bus speeds up to 66 MHz and 83 MHz, the CPC700 allows the Pow- erPC to realize its full potential. To complement this operation, the CPC700 memory subsystem keeps up with the processor by providing an optimized memory controller.
Page 18 For mission critical, zero down time operations, the CPC700 incorporates Error Correction Code (ECC) cir- cuitry with the ability to correct data errors as well as detect address errors. The device also supports the processor’s address and data parity scheme. If processor data parity is not required, the unused pins can be conﬁgured to provide PCI arbitration.
Page 19: Figure 1. System Block Diagram
PowerPC 60x/7xx Processor PCI Devices 60x/7xx Bus PCI arbiter CPC700 Timers 2 UARTs PCI Bus Interrupts SDRAM ROM/SRAM External Peripheral Figure 1. System Block Diagram CPC700 User’s Manual—Preliminary...
Page 20: Cpc700 Block Diagram
The block diagram illustrates the internal and external bus frequencies of the CPC700, given a 66MHz pro- cessor bus. Each of the blocks in the diagram represents a core from the IBM Blue Logic core library. The architecture is based on two primary busses, the Processor Local Bus (PLB) and the On Chip Peripheral Bus (OPB).
Page 21 Processor to PLB Interface The CPC700 provides an interface to attach a 60x or 7xx processor to the internal PLB and to provide the processor with a low latency access path to local memory. Through this interface, the processor may access the PCI bus, local memory, external peripherals, and internal peripherals (UARTs, I2Cs, Timers, and interrupt controller).
Page 22: Table 1. Address Map
- Single-beat PCI conﬁguration reads and writes (type 0 and type 1) - PCI interrupt acknowledge - PCI special cycle • Buffering between PLB and PCI: - PCI target 32-byte write post buffer - PCI target 32-byte read prefetch buffer - PCI master 32-byte write post buffer CPC700 User’s Manual—Preliminary...
Page 23 33MHz PCI bus operation. Memory Controller The CPC700 Memory Controller provides the local PowerPC processor with a low latency access path to local memory and external peripherals. In addition, it supports hardware coherent accesses to the proces- sor’s local memory from the PCI bus.
Page 24 • Peripheral Device pacing with external “Ready”. The CPC700 generates, checks, and corrects ECC bits on their way to and from the memory controller. Write cycles to memory that are less than a word in width require the ECC controller to generate a read cycle to fetch the appropriate word, modify that word, generate the ECC bits, and write the word back out to memory.
Page 25 The CPC700 UARTs are functionally identical to NS16450 in character mode (on power up they will be in this mode). The UARTs can be put into FIFO mode to relieve the processor of excessive software over- head. Here internal FIFOs are activated, allowing 16 bytes (plus three bits per byte of error data in the RCVR FIFO) to be stored in both receive and transmit modes.
Page 26: Table 2. Pll Usage
The CPC700 clocking is controlled by two PLLs that minimize clock skew between the internal latches of the CPC700 and the external devices in the system. PLL1 is only used when the PCI interface is used in asynchronous mode. When in synchronous mode, PLL1 is placed in bypass mode via pin strappings, and the PCI clock input pin must be pulled to ground.
Page 27 JTAG The IEEE 11.49.1 (JTAG) Boundary scan is included to facilitate tester requirements as well as for the support of board level testing and debug. The following JTAG commands are supported by the CPC700 JTAG TAP controller: EXTEST SAMPLE/PRELOAD BYPASS...
Page 28 1-12 CPC700 User’s Manual—Preliminary...
Page 29: Chapter 2. Signal Descriptions
AP1 - [A8 - A15] AP2 - [A16 - A23] AP3 - [A24 - A31] A[0:31] High Address Bus: Input: Represents the physical address of the data to be transferred. Output: Represents the physical address of a snoop operation. CPC700 User’s Manual—Preliminary...
Page 30 Transfer Size: Indicates the data transfer size for the current operation. ARTRY_N Address Retry: This signal is asserted by either the processor or the CPC700 to indicate that the current address tenure needs to be rerun at a later time. TBST_N Transfer Burst: Indicates a burst transfer of four 64-bit double-words on the processor bus.
Page 31: Pci Bus Interface Signals
RST_N PCI RESET: This output may be used as the reset to PCI bus slots when the CPC700 is used as the primary host bridge. This signal will be asserted during three scenarios: Power on Reset: Following the deasertion of SYS_RESET_N, RST_N will remain active for a period of 500us while the internal PLLs lock after which, this signal will be deaserted.
Page 32 GNT_N functions as the Request[0] input from another PCI master device. When the internal PCI arbiter is disabled and an external arbiter is employed, this signal is the Grant input for the CPC700 from the external arbiter. REQ1_N Request[1]: When the internal PCI arbiter is enabled, this signal functions as the Request[1] input from another PCI master device.
Page 33: Memory Interface Signals
DQM inputs of all DIMMs if ECC is used in the system. If ECC is not used, then ECC/DQM[1:7] lines make up the remainder of the 8-bit DQM bus. DQM[0] corresponds to Memory Data Lane 0. During reads, the CPC700 asserts DQM high to cause the SDRAM to tristate the SDRAM output. If DQM is low, the SDRAM drives the data onto the output.
Page 34: Internal Peripherals Interface Signal
ROM_ALE High ROM Address Latch Enable: When accessing a bank which is programmed for ROM, SRAM, or peripheral devices, the 24-bit memory address bus is provided in two cycles. The 12-bit address on pins MA[12,11,9:0] bus must be latched on the ﬁrst cycle in order capture and hold the higher order address bits of the ROM / peripheral address.
Page 35: System Interface Signals
System Clock Input: The system clock input must be one half the frequency and in phase with the local processor and SDRAM clocks. SYS_RESET_N System Reset Input: Resets the CPC700 to its initial default state. The internal reset will remain active for 500us after the SYS_RESET_N signal is deasserted.
Page 36 JTAG probe). Because the boundary scan function of the JTAG port does not work in dd 1.1 of the CPC700, we strongly recommend that this signal be brought out from the solder ball to at least a via, so that a board tester can drive the signal.
Page 37: Chapter 3. Processor Interface
Chapter 3. Processor Interface The processor interface is the portion of the CPC700 that attaches a PowerPC 60x or 7xx processor to the internal PLB and the local memory controller. Through this interface, the processor may access the PCI bus, local memory, and the CPC700’s internal peripherals (UARTs, I C ports, timers, and interrupt control- ler).
Page 38: Processor Interface Registers
NOTE: W.B.=Write Buffer; R.B.=Read Buffer Processor Bus Processor Interface Central W.B. Arbiter/ Memory Controller Snooper Master W.B. W.B. R.B. DCR Slave PLB Master R.B. PLB Slave Interface CONFIG Regs Interface DCR Bus PLB Master PLB Slave Figure 3. Processor Interface Detailed Block Diagram 3.3 Processor Interface Registers Processor interface registers are accessed through an indirect method employing a conﬁguration address register, PIFCFGADR, and a conﬁguration data register, PIFCFGDATA.
Page 39: Processor Interface To Memory, Pci, And Peripherals
3.4 Processor Interface to Memory, PCI, and Peripherals The CPC700 supports 1 full level of addressing pipelining on the processor bus and decodes the target of processor accesses based on the address range of the transfer. All of the processor accesses are decoded as one of the following: •...
Page 40: Table 5. Cpc700 Address Map - Processor View
Table 5. CPC700 Address Map - Processor View (Continued) Processor Address Range Description Address 4G-11M hFF500000 DCR - Configuration Address/Data 4G-10M-1 hFF5FFFFF 4G-10M hFF600000 Internal Peripherals hFF600000 4G-8M-1 hFF7FFFFF hFF7FFFFF 4G-8M hFF800000 System Memory 4G-2M-1 hFFDFFFFF Typically reserved for ROM/External Peripherals...
Page 41: Supported Processor Transfer Types
3.5 Supported Processor Transfer Types Based on signals TT[0:3] (see Table 7), the CPC700 responds to processor initiated transfers by generat- ing a read transaction, a write transaction, or an address-only response. The CPC700 ignores TT[4] when evaluating processor initiated transfers.
Page 42: Processor To Memory
Table 7. Supported Processor Transfer Type Encodings/Response (Continued) Processor Proc Bus CPC700 Response for CPC700 Response for TT[0:3] Operation Transaction Proc to Memory Proc to PLB 1100 TLB invalidate Address only Assert AACK_N, No other response, No PLB transaction 1101...
Page 43: Cpc700 Response For Processor To System Memory Accesses
The following table corresponds to the state of the processor address bus for a given cycle (which may or may not be pipelined) and the corresponding response from CPC700. NOTE: For any of the transactions listed, the internal memory controller interface may be idle or busy (servicing a processor to memory write buffer flush or finishing the data tenure of a previous PCI or processor access to system memory).
Page 44: Processor To Plb Master (Pci Or Internal Peripherals)
3.7 Processor to PLB Master (PCI or Internal Peripherals) The CPC700 supports single beat (8 bytes or less) and burst (32 byte cache line) read and write accesses to the PLB. Processor requests that target PLB space are forwarded to the PLB Master interface which ini- tiates a request on the PLB bus for the associated cycle.
Page 45 Table 11. CPC700 Response to Processor Transactions to the PLB (Continued) Proc-PLB Proc-PLB Proc Read Write Slave Buffer Buffer (Snoop) Response PLB Rd Deallocated Deallocated Snoop ABORT PLB read cycle, ARTRY_N CPU, grant to snooper Pending PLB Rd Deallocated Allocated...
Page 46: Processor - Address Only Cycles
The CPC700 supports all processor generated Address Only cycles. In response to a processor Address Only cycle, CPC700 acknowledges the cycle and takes no other action. As a result, CPC700 does not prop- agate any Address Only cycles beyond the processor bus interface.
Page 47: Processor Bus Arbiter
D.C. - Don’t Care 3.9 Processor Bus Arbiter The CPC700’s processor interface logic contains the processor bus arbiter which controls access to the local processor bus. It arbitrates between processor requests and the internal snoop engine (PCI to mem- ory) requests.
Page 48: Broadcast Snoop Cycles
3.10 Broadcast Snoop Cycles The CPC700 supports PCI accesses to system memory via the PLB Slave interface. Memory coherency is maintained by the internal snoop engine. PCI requests which address system memory are accepted and snooped in the processor's L1 cache before allowing the access. Snoop cycles to the processor are gener- ated on behalf of the PCI interface by the internal snooper.
Page 49: Byte Swapping
3.11 Byte Swapping CPC700 includes support which is designed to ease the use of a Big Endian processor operating in a Little-Endian system. This support includes the ability to swap bytes during read and write accesses to the internal PLB bus from the processor. This mechanism can be used when accessing the PCI bus from the processor.
Page 50: Figure 5. Processor To Plb Big-Endian To Little-Endian Byte Swapping
1-, 2-, 4-, 8-, and 32-byte aligned 64-bit transfers are available as shown in Figure 5. 2 Byte Aligned 1 Byte Aligned (Default-No Swap) Processor 0 1 2 3 4 5 6 7 Processor 0 1 2 3 4 5 6 7 PLB Byte 0 1 2 3 4 5 6 7 PLB Byte...
Page 51: Pci To Memory Byte Swapping
32-bit data as seen from both the PowerPC processor and the PCI bus. As in the default method, bit ordering within bytes is preserved: PCI_BYTE3[31:24] corresponds to CPU/MEM_BYTE0[0:7] and PCI[31:0] = CPU/MEM[0:31] CPC700 User’s Manual—Preliminary 3-15...
Page 52: Pci To Memory Byte Swapping Examples
Figure 7. Alternative Byte Swapping Method Note: As indicated, this swapping occurs only on PCI to local memory accesses. Even if this byte swapping mechanism is enabled, PCI accesses to CPC700 internal PCI conﬁguration registers are not affected. 3.11.2.3 PCI to Memory Byte Swapping Examples To illustrate the two methods of byte swapping which may be used for local memory accesses from the PCI bus, assume the local processor has written a 32-bit value of x’12345678’...
Page 53: Plb Slave Interface To Memory (Pci To Memory)
1 prior to MC request 8W Line 1 x Quad DW (wrap) 1 prior to MC request W Burst DW(s) and/or Quad DW(s) 1 per 32 byte boundary crossed W - Word, DW - Double Word CPC700 User’s Manual—Preliminary 3-17...
Page 54: Cpc700 Response For Pci To Memory Accesses
3.14 Processor to DCR/Conﬁguration Space Access to the CPC700 processor interface and the memory controller is through a dedicated on chip bus called the Device Configuration Register Bus (DCR Bus). DCR access uses an indirect addressing method whereby a configuration address register and a configuration data register are used to address all of the configuration registers in the processor interface and the memory controller.
Page 55 Memory Controller Config data register xFF50_000C DCR configuration bus cycles unpipeline the processor bus interface and trigger the flushing of all CPC700 processor interface write buffers (Processor-PLB and Processor-Memory) before completing. Furthermore, DCR configuration cycles are required to be 4 byte, aligned accesses.
Page 56: Error Handling And Reporting
3.15 Error Handling and Reporting 3.15.1 Processor transfer type errors The processor interface may be enabled to detect and report processor transfer attribute errors. On a processor read, if a transfer attribute error is detected, the processor interface will complete the access and return all 1’s (that is, each bit in the processor data bus will be set to 1) with the transfer acknowledge assertion.
Page 57: Memory Select Error - Processor Access
If detection is enabled via ERREN1[6], the error will be logged by setting ERRDET1[5], the associated pro- cessor address and transfer attributes will not be logged, and if enabled via PRIFOPT1[1], MCP_N will be asserted for a minimum of two clock cycles. CPC700 User’s Manual—Preliminary 3-21...
Page 58: Data Parity Errors
PLB_MErr will be asserted into the 60x-PLB master (by the targeted PLB slave) on any 60x-PLB transfer for which the responding PLB slave encounters an error. In the CPC700, the only PLB slave targets that could assert PLB_MErr into the 60x-PLB master are the PCI interface and the OPB.
Page 59: Pci Writes To Local Memory
• There are no internal registers associated with MCP_REQ. The external logic that asserts MCP_REQ to CPC700 must provide mask and status information. • The MCP_REQ input contains no edge detection logic. The CPC700 has no memory of any previous state of MCP_REQ.
Page 60: Ecc Errors
• CPC700 will not assert MCP_N while MCP_REQ is active unless MCP_N assertion is enabled. If MCP_REQ is active when MCP_N assertion is enabled, then MCP_N will be asserted. • Unlike other processor bus related error sources, when CPC700 samples MCP_REQ asserted, it does NOT disable further error detection.
Page 61: Prifopt1 - Processor Interface Options 1
PLBM_PRI Processor Interface - PLB Master Request Priority This field indicates the PLB request priority associated with 60x to PLB transfers. This field is currently hardcoded to b’11’ indicating the highest priority and is read only. CPC700 User’s Manual—Preliminary 3-25...
Page 62: Errdet1 - Error Detection 1
Enables use of PLBSWRINT region. When the PLB address falls within the 16KB region as programmed into the PLB- SWRINT register, an interrupt will be generated to the CPC700 interrupt controller. System software may separately program the interrupt controller to generate an interrupt to the processor based on this condition or not.
Page 63: Erren1 - Error Detection Enable 1
This bit enables the detection of memory select errors associ- ated with a PLB Master access to system memory. It enables the assertion of Merr by a PLB slave, and the trap- ping of address information in the BESR and BEAR registers. CPC700 User’s Manual—Preliminary 3-27...
Page 64: Cpuerad - Processor Error Address
F_WR_ER_EN Flash Write Error Enable 0 - Detection Disabled 1 - Detection Enabled CPU_APE_EN 60x Address Parity Error Enable 0 - Detection Disabled 1 - Detection Enabled CPU_DPE_EN 60x Data Parity Error Enable 0 - Detection Disabled 1 - Detection Enabled 8:31 Reserved 3.16.4 CPUERAD - Processor Error Address...
Page 65: Plbmifopt - Plb Master Interface Options
1 - Enabled XLR_3_EN Processor-PLB Byte Swap Region 3 0 - Disabled 1 - Enabled PLBS_XL_ PCI to Memory Byte Swapping 0 - Disable - Preserve Byte Lanes 1 - Enable - Swap Byte Lanes 4:31 Reserved CPC700 User’s Manual—Preliminary 3-29...
Page 66: Plbmtlsa1 - Plb Master Byte Swap Region 1 Starting Address
3.16.7 PLBMTLSA1 - PLB Master Byte Swap Region 1 Starting Address PLBMTLSA1 contains the starting address of byte swapping region 1. This starting address identiﬁes the beginning of a region with a 16KB granularity. Address Offset: Width: Reset Value: x0000_0000 Access: Read/Write Name...
Page 67: Plbmtlsa2 - Plb Master Byte Swap Region 2 Starting Address
PLBMTLEA2 contains the ending address of byte swapping region 2. This ending address identiﬁes the ending of a byte swapping translation region with a 16KB granularity. Address Offset: Width: Reset Value: x0000_0000 Access: Read/Write Name Reset Description Value 0:17 XLR_2_EA Processor-PLB Byte Swap Region 2 Ending Address 18:31 Reserved CPC700 User’s Manual—Preliminary 3-31...
Page 68: Plbmtlsa3 - Plb Master Byte Swap Region 3 Starting Address
3.16.11 PLBMTLSA3 - PLB Master Byte Swap Region 3 Starting Address PLBMTLSA3 contains the starting address of byte swapping region 3. This starting address identiﬁes the beginning of a region with a 16KB granularity. Address Offset: Width: Reset Value: x0000_0000 Access: Read/Write Name...
Page 69: Plbsnssa0 - Plb Slave No Snoop Region Start Address
PLBSNSEA0 identiﬁes the ending address of the no-snooping region with a 16KB granularity. Reserved bits are "don’t cares" for address decoding purposes. Address Offset: Width: Reset Value: x7FFF_C000 Access: Read/Write Name Reset Description Value 0:17 NSEA0 7FFFC Snoop Disable Ending Address 18:31 Reserved CPC700 User’s Manual—Preliminary 3-33...
Page 70: Besr - Bus Error Syndrome Register
PCI accesses to system memory. Only Master 1 which corresponds to the PCI interface is used in the CPC700. Master 0 corresponds to the processor interface o itself which will never access its own slave port through the PLB.
Page 71: Bear - Bus Error Address Register
This register is logically part of the PLB Slave interface within the processor interface and contains the ad- dress associated with any errors encountered during PLB Master accesses to system memory. In the CPC700 the only PLB Master which accesses the system memory via the PLB is the PCI interface. Name...
Page 72 3-36 Processor Interface...
Page 73: Chapter 4. Memory Controller
Bank 0 is typically used for the boot ROM. 4.1 Features Synchronous DRAM: • Memory bus operates at the same frequency as the processor bus (up to 66 MHz with CPC700-66 or up to 83 MHz with CPC700-83) • Up to 4 banks (Bank 0 defaults to ROM) •...
Page 74: Memory Controller Block Diagram
• Support for mixing ECC and Non-ECC DIMMs in the same system • ECC checking may be disabled 4.2 Memory Controller Block Diagram A block diagram of the CPC700 memory controller is shown in Figure 8. DCR Bus register outputs...
Page 75: Memory Controller Registers
Memory Bank 1 Ending Address MB2EA Memory Bank 2 Ending Address MB3EA Memory Bank 3 Ending Address MB4EA Memory Bank 4 Ending Address SDTR1 SDRAM Timing register 1 ROM Bank Width FWEN Flash Write Enable ECCCF ECC Conﬁguration CPC700 User’s Manual—Preliminary...
Page 76: Memory Access Arbiter
32 byte aligned address transferring a four doubleword line. 4.5 SDRAM The CPC700 memory controller supports both dual and quad internal bank SDRAMs in 32-bit and 64-bit conﬁgurations (40-bit and 72-bit if using ECC) with fully programmable timing parameters. Both standard and pipelined architecture SDRAMs are supported and the memory controller provides a mechanism to enable/disable read and write with auto-precharge.
Page 77: Initialization Sequence
System: After Reset is deactivated, pause the amount of time indicated in the SDRAM speciﬁcation. - Example: IBM 16MB SDRAM requires 100us pause and 64MB SDRAM requires 200us. Conﬁgure SDRAM related conﬁguration registers (may occur during pause period). Set DC_EN = 1 in the MCOPT1 register to enable the SDRAM controller Step 3 automatically causes the SDRAM Controller to: Issue Precharge command to all banks.
Page 78: Memory Timing Parameter Deﬁnitions
Table 23. Determining Maximum Page Size (Continued) mode 1-3 mode 4 64-bit contiguous column address bits = 9 contiguous column address bits = 8 (72-bit ECC) =512 unique column addresses =256 unique column addresses data width 64-bit = 8 byte data width 64-bit = 8 byte page size = 512 x 8byte = 4KByte page size = 256 x 8byte = 2KByte...
Page 79 Table 24. SDRAM Memory Timing Parameters SD_APGE Auto-Pre- Auto-Precharge enable. When enabled, all SDRAM Read/Write charge Enable accesses will be performed as Read w/Auto-Precharge or Write w/Auto-Precharge. SD_CASL CAS_ Latency Programmable access latency. CPC700 User’s Manual—Preliminary...
Page 80: Sdram Conﬁguration Registers
PCI to memory accesses when using SDRAM. This mapping of the processor’s physical ad- dress to the CPC700’s Bank Address (BA[1:0]) and Memory Address (MA[12:0]) pins is done by the CPC700 on a per bank basis based on the mode settings in the DRAM Addressing Mode (DAM) registers. 4.5.5.1 32-Bit Memory Mapping The following tables specify the organization of the SDRAM as follows: ROW x COLUMN (INTERNAL BANKS).
Page 81 13 x 9 (2) Column *Enables support of 13 x 9 (2). Mode 2 12 x 10 (4) 13 x 10 (2) A7** Column A7** **Enables support of 13 x 10 (2) Mode 3 13 x 9 (4) Column CPC700 User’s Manual—Preliminary...
Page 82: 64-Bit Memory Mapping
Mode 3 13 x 10 (4) Column Mode 3 13 x 11 (4) Column # Column address bit 10 sent out on M11 for 13 x 11 (4) parts. This bit is driven by the SDRAM controller. Mode 4 12 x 8 (2) 13 x 8 (2) 12 x 8 (2) Column...
Page 83 *Enables support of 13 x 9 (2). Mode 2 12 x 10 (4) 13 x 10 (2) A6** Column A6** **Enables support of 13 x 10 (2) Mode 3 13 x 9 (4) Column Mode 3 13 x 10 (4) Column CPC700 User’s Manual—Preliminary 4-11...
Page 84: Precharge Command
Mode 3 13 x 11 (4) Column # Column address bit 10 sent out on M11 for 13 x 11 (4) parts. Mode 4 12 x 8 (4) 13 x 8 (2) 12 x 8 (4) Column 4.5.6 Precharge Command Issuing the Precharge Command instructs the SDRAM to precharge all banks and is generated by the SDRAM controller as needed when Auto-Precharge is disabled as configured by register bit SD_APGE.
Page 85: Self-Refresh Operation
32 or 64-bit width (as set via the SD_WDTH bit in the ECCCF register) and configures the SDRAM for burst of 8 or burst of 4 respectively. Table 26. Mode Set Command Vector 64-bit bus SD_CASL 32-bit bus SD_CASL CPC700 User’s Manual—Preliminary 4-13...
Page 86: Timing Parameters
4.5.9 Timing Parameters 4.5.9.1 SDRAM Timing Diagrams The following timing diagrams are included to illustrate the SDRAM programmable timing parameters only. CLOCK BA(1:0) MA(12) MA(11:7) 00000 MA(6:5) MA(4) SD_CASL MA(3) MA(2:0) RAS_/SD_CS_ SD_PTA min. satisﬁed Min. of 4 CLKs SD_RAS_ SD_CAS_ CAS_/SD_DQM Figure 10.
Page 87: Figure 11. Read Without Auto-Precharge
BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_RAS_ SD_RCD SD_RTP SD_PTA SD_CAS_ CAS_/SD_DQM SD_CASL DATA Figure 11. Read without Auto-Precharge CLOCK BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_RAS_ SD_RCD SD_WTP SD_PTA SD_CAS_ CAS_/SD_DQM DATA Figure 12. Write without Auto-Precharge CPC700 User’s Manual—Preliminary 4-15...
Page 88: Figure 13. Read With Auto-Precharge
CLOCK BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_RAS_ SD_RCD SD_RTP SD_PTA SD_CAS_ CAS_/SD_DQM SD_CASL DATA * Auto-Precharge Begins Figure 13. Read with Auto-Precharge CLOCK BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_RAS_ SD_RCD SD_WTP SD_PTA SD_CAS_ CAS_/SD_DQM DATA * Auto-Precharge Begins Figure 14. Write with Auto-Precharge 4-16 Memory Controller...
Page 89: Figure 15. Precharge All Command
CLOCK BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_PTA SD_RAS_ SD_CAS_ CAS_/SD_DQM Figure 15. Precharge All Command CLOCK BA(1:0) MA(12:0) RAS_/SD_CS_(0,4) RAS_/SD_CS_(1,5) RAS_/SD_CS_(2,6) SD_RFTA RAS_/SD_CS_(3,7) SD_RAS_ SD_CAS_ CAS_/SD_DQM Figure 16. CAS-before-RAS Refresh CPC700 User’s Manual—Preliminary 4-17...
Page 90: Figure 17. Self-Refresh Entry/Exit
CLOCK SD_PTA BA(1:0) MA(12:11) MA(10)/AP MA(9:0) RAS_/SD_CS_ SD_PTA SD_RAS_ SD_CAS_ CAS_/SD_DQM Self Refresh Exit Precharge all (if necessary) Figure 17. Self-Refresh Entry/Exit 4-18 Memory Controller...
Page 91: Cpu-To-Memory Timing Diagrams
4.5.9.2 CPU-to-Memory Timing Diagrams Figure 18. CPU Read - Read CPC700 User’s Manual—Preliminary 4-19...
Page 92: Figure 19. Cpu Read - Write
Figure 19. CPU Read - Write 4-20 Memory Controller...
Page 93: Figure 20. Cpu Write - Read
Figure 20. CPU Write - Read CPC700 User’s Manual—Preliminary 4-21...
Page 94: Figure 21. Cpu Write - Write
Figure 21. CPU Write - Write 4-22 Memory Controller...
Page 95: Pci-To-Memory Timing Diagrams
4.5.9.3 PCI-to-Memory Timing Diagrams Figure 22. PCI Continuous Read Burst CPC700 User’s Manual—Preliminary 4-23...
Page 96: Figure 23. Continuous Write Burst
Figure 23. Continuous Write Burst 4-24 Memory Controller...
Page 97: Figure 24. Pci Short Burst Read - Pci Short Burst Read
Figure 24. PCI Short Burst Read - PCI Short Burst Read CPC700 User’s Manual—Preliminary 4-25...
Page 98: Figure 25. Pci Short Burst Read - Pci Short Burst Write
Figure 25. PCI Short Burst Read - PCI Short Burst Write 4-26 Memory Controller...
Page 99: Miscelaneous Memory Timing Diagrams
4.5.9.4 Miscelaneous Memory Timing Diagrams Figure 26. CPU Line Read-PCI Burst Read CPC700 User’s Manual—Preliminary 4-27...
Page 100: Figure 27. Cpu Line Read To Pci Write Burst
Figure 27. CPU Line Read to PCI Write Burst 4-28 Memory Controller...
Page 101: Rom/Peripheral Controller
Bit 0 of the peripheral address bus is the low order bit for the device width programmed for the active CPC700 bank. If the width is programmed as byte, then the address bus carries byte addresses. If the width is programmed as doubleword (8 byte), then the address bus carries doubleword addresses (bit 0, the LSb of the peripheral bus, references a doubleword, and no byte address exists on the bus).
Page 102: Reads
programmed as a doubleword device, any byte may be accessed with only one read occurring on the bus, but valid data exists only at the bytes on doubleword boundaries. Thus, when programmed as doubleword, instruction fetching cannot occur from the NVRAM. 4.6.2 Reads The internal memory data interface to the ROM controller is 64 bits wide independent of the ROM device width.
Page 103: Shared Address/Data/Control
4.6.5 Device Attachment Devices must be attached left justiﬁed with bit 0 as the MSB on the ROM/Peripheral bus as indicated in Table 30. CPC700 User’s Manual—Preliminary 4-31...
Page 104: Rom / Peripheral Conﬁguration Registers
The CPC700 ROM controller has programmable timings that allow for ROM, SRAM, and peripheral sup- port. An external READY input is provided to allow for device-paced transfers on both READs and WRITEs.
Page 105: Rom/Peripheral Attachment
The CPC700 is inherently a Big-Endian system. ROM and peripherals which are typically speciﬁed as litttle endian should be connected with their MSB of their data bus attached to the CPC700’s MSB. That is for a 64-bit ROM, CPC700 M_DATA(0) should connect to ROM(63) and CPC700(63) connects to ROM(0).
Page 106: Rom Timing Diagrams
4.6.8 ROM Timing Diagrams Clock THDRD THDWR 1+TWT READ# WRITE# CSON OEON WEOFF WEON OEON W_DATA Data Sampled On READS R_DATA Figure 29. Single Read/Write (General) 12 13 14 15 16 17 21 22 Clock THDRD 1+FWT 1+NWT 1+NWT READ# WRITE# CSON OEON...
Page 107: Figure 31. Non-Burst Read
READ# WRITE# R_DATA Figure 31. Non-Burst Read clock READ# WRITE# W_DATA READY Figure 32. Single Write, Synchronous Ready Enabled CPC700 User’s Manual—Preliminary 4-35...
Page 108: Figure 33. Single Write, Asynchronous Ready Enabled
clock READ# WRITE# W_DATA READY Figure 33. Single Write, Asynchronous Ready Enabled clock READ# WRITE# R_DATA READY Figure 34. Non-Burst Read, Synchronous Ready Enabled 4-36 Memory Controller...
Page 109: Figure 35. Non-Burst Read, Synchronous Ready Enabled
READ# WRITE# R_DATA READY Figure 35. Non-Burst Read, Synchronous Ready Enabled clock READ# WRITE# R_DATA READY Figure 36. Burst Mode Read, Asynchronous Ready Enabled CPC700 User’s Manual—Preliminary 4-37...
Page 110: Ecc
clock READ# WRITE# R_DATA READY Figure 37. Burst Mode Read, Asynchronous Ready Enabled 4.7 ECC The ECC module uses a 64 bit SEC/DED code which has been modified to support detection of single bit address errors. The module supports a 64 data bit / 8 check bit interface, as well as a dual 32 data bit / 8 check bit interface (the dual 32-bit interface is used when the memory controller has an external 32 data bit memory interface).
Page 111: Ecc Registers
The ECC Conﬁguration register is used to conﬁgure the various modes of the ECC controller. If ECC is implemented in a system, then the CPC700 will provide eight ECC bits and a single DQM output since all memory transactions will be full 64-bit transfers (or 32-bit if 32-bit mode is selected). Write transactions of less than the full data width will generate a read-modify-write cycle in order to generate ECC across the entire data width.
Page 112: Ecc Erorrs And Interrupts
MCP enable bit (bit 1) of the PRIFOPT1 register is set. Correctable ECC errors will be reported to the CPC700’s interrupt controller via IRQ 0. System software may seperately program the interrupt controller to generate an interrupt to the processor based on this condition or not. See Section Chapter 10., “Interrupt Controller”...
Page 113: Dynamic Ecc Testing
Byte Enable Bit Range A[29]=0 A[30:31]=00 0:7 (MSB) A[29]=0 A[30:31]=01 8:15 8:15 A[29]=0 A[30:31]=10 16:23 16:23 A[29]=0 A[30:31]=11 24:31 24:31 A[29]=1 A[30:31]=00 32:39 32:39 A[29]=1 A[30:31]=01 40:47 40:47 A[29]=1 A[30:31]=10 48:55 48:55 A[29]=1 A[30:31]=11 56:63 56:63 (LSB) CPC700 User’s Manual—Preliminary 4-41...
Page 114: Table 37. Local Processor To Pci Data Flow
The dataflow for local processor to PCI in Table 37. assumes that byte swapping is disabled. See Section 3.11, “Byte Swapping” for a discussion on how byte swapping affects dataflow between the processor and the PCI bus as well as between the PCI bus and local memory. Table 37.
Page 115: Memory Controller Register Description
Note: In the tables of register field descriptions throughout this specification, some bits are shown shaded. Those bits are reserved in the CPC700. Reading of reserved bits will produce unpredictable values. Soft- ware must use appropriate masks to extract the desired bits. Writes must preserve the values of reserved bit positions by first reading the register, merging the new values, and writing the result back.
Page 116 4.9.1.1 MCOPT1 - Memory Controller Options 1 Address Offset: Width: Reset Value: x0000_0001 Access: Read/Write This register sets the options for the memory controller. Name Reset Description Value DC_EN SDRAM Controller enable: 0 - Disable 1 - Enable This bit enables the portion of the memory controller which ac- cesses SDRAM.
Page 117: Mben - Memory Bank Enable
Memory bank 4 enable. 0 - Disable 1 - Enable 5:31 Reserved 4.9.1.3 MEMTYPE - Installed Memory Type Address Offset: Width: Reset Value: x0000_0000 Access: Read/Write This register must be configured for each memory bank that is enabled. CPC700 User’s Manual—Preliminary 4-45...
Page 118: Mb0Sa - Memory Bank 0 Starting Address
Name Reset Description Value MT_0 Bank 0 Memory: 00 - ROM 01 - DRAM 1x - RESERVED These bits default to 00 to enable boot ROM in bank 0. MT_1 Bank 1 Memory: 00 - ROM 01 - DRAM 1x - RESERVED MT_2 Bank 2 Memory: 00 - ROM...
Page 119: Mb0Ea - Memory Bank 0 Ending Address
4.9.1.7 MBxEA - Memory Bank 1-4 Ending Address Address Offset: x5C, 60, 64, 68 Width: Reset Value: x0000_0000 Access: Read/Write These registers contain the ending addresses for banks 1 through 4. The minimum granularity for installed memory is 1M Byte. CPC700 User’s Manual—Preliminary 4-47...
Page 120: Sdram Speciﬁc Conﬁguration Registers
Name Reset Description Value 0:11 MBxEA Memory Bank x ending address. Bit 0 corresponds to CPU A0, bit 11 corresponds to CPU A11. 12:31 Reserved 4.9.2 SDRAM Speciﬁc Conﬁguration Registers 4.9.2.1 SDTR1 - SDRAM Timing Register 1 Address Offset: Width: Reset Value: x0004_9C0A Access:...
Page 121 110 - 10 CLK 111- Reserved 30:31 SD_RCD SDRAM RAS to CAS delay. Indicates the number of clock cycles from Activate Command to Read or Write Command. 0x - Reserved 10 - 2 CLK 11 - 3 CLK CPC700 User’s Manual—Preliminary 4-49...
Page 122: Rwd - Bank Active Watchdog Timer
4.9.2.2 RWD - Bank Active Watchdog Timer Address Offset: Width: Reset Value: xFF00_0000 Access: Read/Write This register limits the maximum internal bank active time for SDRAM. This register represents the maxi- mum amount of time in units of eight processor bus clock cycles. Name Reset Description...
Page 123: Dam - Dram Addressing Mode
00 - Mode 1 01 - Mode 2 10 - Mode 3 11 - Mode 4 DAM_4 Bank 4 Addressing mode: 00 - Mode 1 01 - Mode 2 10 - Mode 3 11 - Mode 4 10:31 Reserved CPC700 User’s Manual—Preliminary 4-51...
Page 124: Rom Speciﬁc Conﬁguration Registers
4.9.3 ROM Speciﬁc Conﬁguration Registers 4.9.3.1 RPBxP - ROM/Peripheral Bank Parameters Address Offset: xE0, E4, E8, EC, F0 Width: Reset Value: xFC03_F8F0 Access: Read/Write These configuration registers consist of one register per bank with each register being used to configure the access modes and timings on a per-bank basis. The controller has programmable timings that allow for ROM, SRAM, and peripheral support.
Page 125 Initial wait states on subsequent accesses of all burst trans- fers. The number of cycles from address valid to the next address valid including the time for latching the ROM/Peripheral ad- dress is 1+FWT for the first access to a bursting device. 28:31 Reserved CPC700 User’s Manual—Preliminary 4-53...
Page 126: Rbw - Rom Bank Width
4.9.3.2 RBW - ROM Bank Width Address Offset: Width: Reset Value: x0000_0000 Access: Read/Write This register must be configured to indicate the width of the installed ROM or external peripheral in each bank. Name Reset Description Value 64N8_0 ROM Bank 0 width. 00 - 8 bit 01 - 16 bit 10 - 32 bit...
Page 127: Fwen - Flash Write Enable
Bank 2 Flash write enable. 0 - Disable 1 - Enable FLSHWEN_3 Bank 3 Flash write enable. 0 - Disable 1 - Enable FLSHWEN_4 Bank 4 Flash write enable. 0 - Disable 1 - Enable 5:31 Reserved CPC700 User’s Manual—Preliminary 4-55...
Page 128: Ecc Speciﬁc Registers
When a BANKn enable is set to 0, the con- troller will use the byte selects (DQMs) to perform the write. This capability allows the CPC700 to support mixing of ECC and non-ECC banks. In systems which support ECC and therefore have a single DQM output, less than 8-byte writes to non-ECC banks will result in a read-modify-write operation.
Page 129 0 - Correction Disabled 1 - Correction Enabled ECC_BANK3_CEN ECC Bank 3 Correction Enable 0 - Correction Disabled 1 - Correction Enabled ECC_BANK4_CEN ECC Bank 4 Correction Enable 0 - Correction Disabled 1 - Correction Enabled 21:31 Reserved CPC700 User’s Manual—Preliminary 4-57...
Page 130: Eccerr - Ecc Error Register
MCP enable bit (bit 1) of the PRIFOPT1 register is set. Correctable ECC errors will be reported to the CPC700’s interrupt controller via IRQ 0. System software may seperately program the interrupt controller to generate an interrupt to the processor based on this condition or not. See Section Chapter 10., “Interrupt Controller”...
Page 131 1 - Error Occurred in Bank 2 BNK3ERR Bank 3 Error 0 - No Error 1 - Error Occurred in Bank 3 BNK4ERR Bank 4 Error 0 - No Error 1 - Error Occurred in Bank 4 21:31 Reserved CPC700 User’s Manual—Preliminary 4-59...
Page 132 4-60 Memory Controller...
Page 133: Chapter 5. Pci Interface
This interface is fully compliant with version 2.1 of the PCI Speciﬁcation. The PCI Interface communicates with the 6xx/7xx processor and local memory via the Processor Local Bus (PLB) which is internal to the CPC700. The PCI Interface is both a slave and a master on the PLB. 5.2 Features •...
Page 134: Pci Bridge Block Diagram
5.3 PCI Bridge Block Diagram The PCI Interface macro block diagram is shown in Figure 38. PLB Slave PLB Master CONFIG PLB Slave PLB Master Reg Block W.B. R.B. Interlock W.B. R.B. PCI Master PCI Target Async Arbiter (Optional) R.B. = Read Buffer W.B.
Page 135: Pci Interface Registers
Description PCIVENDID 01 - 00 Vendor ID PCIDEVID 03 - 02 Device ID PCICMD 05 - 04 Command Register PCISTATUS 07 -06 Status Register PCIREVID Revision ID PCIINTCLS Interface Class PCISUBCLS Sub-Class Code PCIBASECC Base Class Code CPC700 User’s Manual—Preliminary...
Page 136: Pci Interface Address Maps
Table 40.PCI Interface Conﬁguration Register Offsets (Continued) PCI Conﬁg Register Offset Description PCICACHELS Cache Line Size PCILATTIM Latency Timer PCIHDTYPE Header Type PCIBIST Built In Self Test Control PCIBAR0 Unused BAR 0 PCIPTM1BAR PTM 1 BAR PCIPTM2BAR PTM 2 BAR Reserved 1C - 27 Unused BARs...
Page 137: Table 41. Plb Address Map
PCI Memory - Range 0 h0000_0000_0000_0000 hFFFF_FFFF_FFFF_FFFF hF7FF_FFFF PMM 0 registers map a region in PLB space to a region in PCI memory space. The address ranges are fully program- mable and support both 32-bit and 64-bit PCI addresses. CPC700 User’s Manual—Preliminary...
Page 138: Pci Master Map (Pmm) Conﬁguration
Table 41. PLB Address Map (Continued) PLB Address Range Description PCI Address h8000_0000- PCI Memory - Range 1 h0000_0000_0000_0000 hFFFF_FFFF_FFFF_FFFF hF7FF_FFFF PMM 1 registers map a region in PLB space to a region in PCI memory space. The address ranges are fully program- mable and support both 32-bit and 64-bit PCI addresses.
Page 139: Pci Address Map
The size of each PTM is programmable, using the Memory Size/Attribute registers. The size is a power of two, and is a minimum of 4KB and a maximum of 4GB. The PLB and PCI address spaces for each PTM are aligned to this size. CPC700 User’s Manual—Preliminary...
Page 140: Pci Target Interface (Plb Master)
This section describes how the CPC700 handles read and write requests from a PCI master device. The CPC700 responds as a PCI target to PCI Memory transactions when the PCI address in within one of the two PTM ranges and the Memory Access bit of the PCI Command Register is enabled. The CPC700 responds by claiming the PCI cycle, and mastering a cycle on the PLB.
Page 141: Handling Of Reads From Pci Masters
5.6.2 Handling of Reads from PCI Masters The CPC700 responds to PCI Memory Read, Memory Read Line and Memory Read Multiple commands. The PCI interface initiates all PLB reads as single-beat or word burst transfers. Memory Read generates a PLB single-beat read while Memory Read Line and Memory Read Multiple generate PLB word bursts. In the case of Memory Read Line, the PCI interface encodes a burst length on the M[x]_BE pins of the PLB, which corresponds to the number of words from the start address to the end of a 32-byte boundary.
Page 142: Read Prefetching
The PCI interface responds to Memory Write and Memory Write and Invalidate commands. All PCI master writes are posted. A 32 byte write buffer is used for this purpose (in the CPC700, the memory controller also has a 32-byte write post buffer, thus a total of 64 bytes can be write posted). The write buffer accepts up to two separate PCI write transactions.
Page 143: Byte Enable Handling
2 bytes because that is the maximum size possible for a PCI data phase with non-contiguous byte enables. • When a PCI data phase with contiguous (but not all active) byte enables is detected, the CPC700 con- tinues accepting data, but that data phase is converted into one single beat, 1-3 byte PLB write, inde- pendent of previous PCI data phases.
Page 144 Table 43.PCI Interface Responses to PCI Requests (Continued) PCI Transaction PLB Size PCI, PLB Bus PLB Response PCI Interface Action Action memory read single-beat read PCI: DEVSEL_ PLB_M[x]Rearbi- retry PCI trate PLB: request bus memory read line word burst read PCI: DEVSEL_ PLB_M[x]AddrAck transfer PCI burst...
Page 145: Pci Master Interface (Plb Slave)
The term “single beat” or “1-4 byte” in reference to PLB transfers refers to the M[x]_size=0000b transac- tion type. The CPC700 initiates the following commands as a PCI master: • I/O Read and I/O Write This command is generated in response to PLB 1-4 byte read or write requests that decode to one of the two PCI I/O spaces.
Page 146: Plb Slave Read Handling
This command is generated in response to a PLB 1-4 byte write to address FED0_0000h. As PCI target the CPC700 accepts Memory Write and Invalidate (MWI) on incoming transactions. But as PCI master it never initiates Memory Write and Invalidate (MWI) transactions. All PCI memory writes are performed with Memory Writes.
Page 147: Plb Slave Write Post Buffer
(Note that in the CPC700, the CPU interface logic also contains a two-entry, write post buffer. Thus a total of four writes can be posted between the CPU and the PCI bus.) The buffers are not snooped, and are always completed on the PCI bus in the same order as they are received on the PLB bus.
Page 148: Aborted Plb Requests
Table 44.PCI interface Responses to PLB Requests (Continued) PLB Direction PCI Address PLB, PCI Bus PCI Response PCI interface Action and Size Space Action read burst, any memory, I/O, PLB: none (not sup- none size conﬁguration or ported) int. ack. PCI: none write, 1-4 byte memory, I/O,...
Page 149: Other Bridge Functions
Rearb PLB master 5.8.2 Completion Ordering The CPC700 implements the following completion ordering rules: PCI master writes are accepted if there is room in the PCI write post buffer. New PCI master reads are accepted if there is no delayed read (DRR or DRC) in progress: If PCI write post buffer is empty, then begin a connected tenure read, resulting in: Read completes connectedly.
Page 150: Pci Producer-Consumer Model
Various options are available for selecting PCI operating frequencies through the use of strapping pins where pullup or pulldown resistors on certain CPC700 I/O signals are read during system reset. The strapping pins and the corresponding frequency modes are indicated in Table 46.
Page 151: Bridge Conﬁguration
20%. Also, disconnects occur more frequently. 5.9 Bridge Conﬁguration The CPC700 has two sets of conﬁguration registers for conﬁguring the PCI interface, handling errors, and reporting status. The Local Conﬁguration Registers control PLB related functions, and can only be accessed by the processor.
Page 152: Pci Interface Local Conﬁguration Register Descriptions
Note: The Little-Endian to Big-Endian conversion may also be accomplished through the use of the byte swapping region registers of the CPC700’s processor interface. See Section 3.11 “Byte Swapping” and Section 3.16.6 “PLBMIFOPT - PLB Master Interface Options” for information on using the CPC700’s byte swapping capabilities.
Page 153: Pmm 0 Mask/Attribute
(least signiﬁcant) bits of the PCI address are passed through from the PLB address. Only bits 31:12 are writable; bits 11:0 are always zero. 5.9.1.4 PMM 0 PCI High Address PLB Address: FF40_000Ch Width: 32 bits Reset Value: Undeﬁned CPC700 User’s Manual—Preliminary 5-21...
Page 154: Pmm 1 Local Address
This register deﬁnes the high 32 bits of the PCI address that is generated in response to PLB access to range 0. If this register is greater than zero the CPC700 generates a Dual Address cycle, using the value in this register as the high 32 bits of the PCI address.
Page 155: Pmm 2 Local Address
32 bits Reset Value: Undeﬁned Access: Read/Write This register deﬁnes the high 32 bits of the PCI address that is generated in response to PLB access to range 2. See PMM 0 PCI High Address for details. CPC700 User’s Manual—Preliminary 5-23...
Page 156: Ptm 1 Memory Size/Attribute
5.9.1.13 PTM 1 Memory Size/Attribute PLB Address: FF40_0030h Width: 32 bits Reset Value: Undeﬁned Access: Read/Write This register deﬁnes the size and attributes of the region of PCI Memory space that is mapped to local (PLB) space through PTM 1 (see Table 48.). It affects the way PCI Conﬁguration register PTM 1 BAR works.
Page 157: Ptm 2 Local Address
PTM 2. See PTM 1 Local Address for details. 5.9.2 PCI Conﬁguration Register and Cycles The processor can generate Conﬁguration cycles on the PCI bus and access the CPC700 PCI conﬁgura- tion registers using the PCICFGADR and PCICFGDATA registers that are found in PLB address space.
Page 158: Pci Conﬁguration Address Register (Pcicfgadr)
5.9.3 PCI Interface Conﬁguration Registers These registers can be accessed by both the processor and the PCI (if enabled). They are accessed by the PCI with Conﬁguration Type 0 cycles when the IDSEL input of the CPC700 is active. 5-26...
Page 159: Pci Vendor Id Register
The vendor ID register is a 16-bit register used to identify the manufacturer of the PCI device. This register is 1014h (index 00h = 14h, index 01h = 10h) at reset. This is the vendor ID assigned for all IBM-produced PCI devices.
Page 160: Table 50.Pci Command Register Bits
0 when read. Memory Access Controls the CPC700’s response as a PCI Memory target. A value of 1 enables the CPC700 to respond as a target. This bit is 0 (disabled) at reset. PCI Master Enable Enables the CPC700 to master cycles on the PCI bus.
Page 161: Pci Status Register
Indicates that the device is capable of running at 66 MHz. The CPC700 can be conﬁgured to run at 33MHz or 66MHz. This bit is a 0 at reset. The local processor should write this bit to 1 if the CPC700 is conﬁgured for 66MHz PCI operation.
Page 162: Pci Revision Id Register
The revision ID register is an 8-bit register used to hold the current incremental revision numberof the PCI interface. The reset value is the version of the PCI interface as well as the revision level of the CPC700. Tthe local CPU (PLB master) has read/write access to this register.
Page 163: Pci Cache Line Size
Reset Value: Access: Read The PCI cache line size register determines the size of a PCI cache line. The CPC700 does not support a PCI cache, therefore this register is read-only and returns 00h when read. 5.9.3.8 PCI Latency Timer...
Page 164: Pci Built-In Self Test (Bist) Control
Reset Value: Access: Read The PCI BIST register is used for control and status of BIST. The CPC700 does not implement BIST, there- fore this register is read-only and returns 00h when read. 5.9.3.11 PCI Base Address Register 0 (PCIBAR0)
Page 165: Pci Base Address Register 2 (Pciptm2Bar)
The subsystem ID register is a 16-bit register used to hold the device ID of the subsystem or add-in board. Note: the Device ID register holds the device ID for the CPC700, which can be used in many different designs.
Page 166: Pci Subsystem Vendor Id Register
Address offset: 3Dh Width: Reset Value: Access: Read The PCI interrupt pin register tells which PCI interrupt line the device uses.The CPC700 does not generate PCI interrupts, therefore this register is read-only and returns 00h. 5.9.3.21 PCI MIN_GNT Address offset: 3Eh Width:...
Page 167: Pci Max_Lat
Access: Read The PCI bus number register is used to identify the number of the PCI bus controlled by the CPC700. The CPC700 is not a PCI to PCI bridge, therefore this register is read-only and returns 00h when read.
Page 168: Pci Arbiter Control
Access: Read/Write The CPC700 PCI arbiter provides arbitration for up to 6 devices at PCI speeds up to 33Mhz. It is enabled/ disabled based on the boot strapping of the CPC700 TT[4] signal. See Section 6.4 “Power on Reset Pin Strapping Options”...
Page 169: Error Enable
This bit enables the detection of master aborts when the CPC700 Enable is the master during an error condition. If this bit is 1, the CPC700 is enabled to drive Sl[x]_MErr on the PLB bus in response to a master abort. If this bit is 0, driving of Sl[x]_Merr in response to master abort is masked.
Page 170: Error Status
SERR# Asserted on This bit is set when the CPC700 asserts PCI_SERR# on the PCI Received MErr bus in response to the PCI interface receiving PLB_MErr while PLB master.
Page 171: Plb Slave Error Syndrome Register (Sesr)
ﬁelds for that master until the MxFL ﬁeld is cleared. If the PLB_lockerr signal is low for the above situation, the error will be reported and the MxFL ﬁeld will not be set. Additional errors will also be reported. CPC700 User’s Manual—Preliminary 5-39...
Page 172: Table 57.Slave Error Syndrome Register Bits
Name Description 19:0 Reserved M1AL Master 1 (the PCI interface in the CPC700) SEAR Address Lock 0 - SEAR1 Unlocked 1 - SEAR1 Locked M1FL Master 1 (the PCI interface in the CPC700) SESR Field Lock 0 - SESR Unlocked...
Page 173: Plb Slave Error Address Register 0 (Sear0)
Table 57.Slave Error Syndrome Register Bits (Continued) Bit(s) Name Description 31:29 M0ET Master 0 (60X-PLB interface in the CPC700) Error Type 000 - No Error 001 - Parity Error 01x - Reserved 100 - Reserved 101 - Non-conﬁgured Bank Error 11x - Reserved 5.9.3.31 PLB Slave Error Address Register 0 (SEAR0)
Page 174: Pci Initial Target Latency Timer Duration
PCI Bridge are NOT reset by this bit. External Write to PCI When an external PCI master writes to the PCI Command register, Command Interrupt this bit is set and an interrupt is generated to the CPC700 interrupt controller (IRQ 2). 15:14 Reserved Reserved, always read as 0.
Page 175: Pci Subsequent Target Latency Timer Duration
5.10 Error Handling 5.10.1 Introduction The CPC700’s PCI Interface supports the detection and reporting of several types of errors. The errors are reported to the PLB or the PCI and status information is saved in the conﬁguration register set so that error type determination can be done.
Page 176: Error Descriptions
0011 16-word line read/write Memory Upon detection of this error, the CPC700 will set the PLB Unsupported Transfer Type bit of the Error Status Register (bit 0). 5.10.3.2 PCI Master Abort This error is generated by the CPC700’s PCI master when no target responds with PCI_DEVSEL# within the required time-out window and error detection is enabled.
Page 177: Pci Target Abort Received While Pci Master
5.10.3.4 PCI Target Data Bus Parity Error Detection This error is generated when the CPC700’s PCI target detects a data bus parity error on write data from a PCI master doing a write cycle to PLB memory. PCI uses even parity.
Page 178: Pci Master Data Bus Parity Error Detection
This error is generated when a data bus parity error is detected on the PCI bus during a cycle which is mastered by the CPC700’s PCI master. The CPC700’s PCI master will check parity on read cycles and sample PCI_PERR# on write cycles. The bridge PCI master may assert PCI_PERR# if it detects a parity error on a read as explained below.
Page 179: Plb Master Plb_Merr Detection
PLB_MErr detection. If bit 5 is set, the bridge PCI target will execute a target abort. If bit 4 is set, the CPC700 PCI target will assert PCI_SERR# and allow the transaction to continue. If both bits 4 and 5 are set, the bridge PCI target will both target abort and assert PCI_SERR#.
Page 180: Example Address Map Setup
Figure 43. shows the desired address map. System memory resides from 0 to 0FFF_FFFFh in the CPU/ PLB address space. It is accessible from the PCI in the same address space (the CPC700 as a memory target) as defined by PTM1/BAR1. PTM2/BAR2 is not used and disabled in this example. The CPU/PLB master has two spaces in which to access PCI Memory space.
Page 181: Figure 43.Example Address Map
Memory (PLB) Space 9400_0000 Prefetchable PCI Targets PMM1 8C00_0000 9000_0000 8800_0000 8800_0000 PMM0 Non-Prefetchable PCI Targets 8000_0000 8000_0000 1000_0000 1000_0000 PTM1/BAR1 Memory Figure 43.Example Address Map CPC700 User’s Manual—Preliminary 5-49...
Page 182: Other Registers That Must Be Initialized
5.11.1.4 Target Bridge Initialization The CPC700 can also respond as a config target; however, it only responds as a config target when its ID- SEL pin is attached (rather than pulled inactive). This is done when the CPC700 is not the primary (host) PCI bridge.
Page 183 Config Enable bit: • The address map (see Section 5.11.1.1 “Address Map Initialization” ) • PCI Vendor ID • PCI Device ID • PCI Revision ID • PCI Class • PCI Subsystem ID • PCI Subsystem Vendor ID. CPC700 User’s Manual—Preliminary 5-51...
Page 184 5-52 PCI Interface...
Page 185: Chapter 6. Clock, Power Management, And Reset
See Section 6.3.2, “Internal Peripheral Reset Control”. The system designer must ensure that the RESET_OUT_N output from the CPC700 does not cause the SYS_RESET_N input to the CPC700 to be driven low. This would cause the tuning bits to be reset to their factory defaults.
Page 186: Uart Serial Clock
6.5.5, “PLL Tuning Control Register (CPRPLLTUNE)” for details. • RST_N is intended to be used as the PCI reset when the CPC700 is the main system host bridge. In addition to being activated during power-on reset, it may also be activated by writing to bit 12 of the...
Page 187: Reset Connectivity
As shown in Figure 45, a typical reset system is composed of several elements. The reset resources (push-button, power supply supervisor, power-on reset, etc.) drive an active low signal into the SYS_RESET_N input of the CPC700. The CPC700 activates the RESET_OUT_N signal from the asser- tion of SYS_RESET_N until 500 µsec. after the deassertion of SYS_RESET_N.
Page 188: Changes From Earlier Documentation
The RESET_OUT_N signal is ANDed with the HRESET# output of the RISCWatch probe, allowing either the CPC700 or the RISCWatch probe to reset the CPU. Since the CPC700 is not reset by a RISCWatch HRESET#, there is no need to extend HRESET# to the CPU.
Page 189: Table 63. Pci Frequency Modes
Async 49 - 67 MHz pulldown pullup pullup Sync (2:1) 25 - 35 MHz pullup don’t care pulldown The status of the pin strapping may be read through the register shown in Table 69.. CPC700 User’s Manual—Preliminary...
Page 190: Cpr Registers
Read/Write This register can be used to reset the CPC700’s UART, IIC, and GPT internal peripherals. Note that setting a peripheral’s reset bit in the CPRRESET register will hold the peripheral in a reset state until its reset bit is cleared (written to a logic 0).
Page 191: Gpt Capture Event Generation Register (Cprcaptevnt)
Timers” for additional information. After triggering an event, these bits must be reset to their non-active val- ues before another capture event can be triggered. When enabled in the CPC700’s interrupt controller, these events can be used to interrupt the processor.
Page 192: Pll Conﬁguration Access Register (Cprpllaccess)
22:25 PLL1_MULT 0001 0001 PLL 1 Multiplication Factor 26:31 PLL1_TUNE 001111 001111 PLL 1 Tuning Bits Note: If changes from the default values are required, contact your IBM representative for proper values for this register. Clock, Power Management, and Reset...
Page 193: Strapping Pin Register (Cprstrapread)
0 - Enable Asynchronous PCI Mode 1 - Enable Synchronous PCI Mode DQMNECC Select either DQM[1:7] or ECC[1:7] to be muxed on ECC/DQM lines (Pin GBL_N) 0 - ECC[1:7] 1 - DQM[1:7] 6:31 Reserved - Reads return 0 CPC700 User’s Manual—Preliminary...
Page 194 6-10 Clock, Power Management, and Reset...
Page 195: Chapter 7. Uart
The frequency of the UART serial clock is the CPC700’s SYS_CLOCK divided by 4. For example, if the CPC700’s SYS_CLOCK is 33.33 MHz, then the UART serial clock is 8.33 MHz. A programmable baud rate...
Page 196: Functional Description
-1) and generates the 16x clock. Baud rate (bits/s) = (CPC700 SYS_CLOCK / 4) / (16 x Decimal Divisor) • Receiver uses 5-way oversampling as follows: it samples each serial bit ﬁve times, and if at least three of the samples are 1’s, the bit is determined to be a 1, otherwise it is a 0 •...
Page 197: Uart Register Description
The DLAB (Divisor Latch Access Bit) bit of the UARTxLCR controls the function accessed through registers FF60_0X00 and FF60_0X01. When DLAB is 0 access is enabled to the Receiver/Transmitter registers and the Interrupt Enable register. When DLAB is a 1 access is enabled to the Divisor Latch registers. CPC700 User’s Manual—Preliminary...
Page 198: Uart Register Summary
7.2.1 UART Register Summary The system programmer may access any of the UART registers summarized in Table 71. via the processor. These registers control the UART operations including transmission and reception of data. Each register bit in the table has its name and reset state shown. Table 71.
Page 199: Line Control Register
Bit 6 = 1 speciﬁes seven bits as length for each transmitted or received serial character. Bit 7 = 0 Bit 6 = 1 speciﬁes eight bits as length for each transmitted or received serial character. Bit 7 = 1 CPC700 User’s Manual—Preliminary...
Page 200: Line Status Register
When the THRE enable (bit 6 in the IER) is set to logic 1, the UART will issue an interrupt to the CPC700 interrupt controller. This bit is set to logic 1 when a character is transferred from the THR to the transmitter shift register.
Page 201: Fifo Control Register
Transmitter FIFO reset. The 1 that is written into this position is self-clearing. Transmitter FIFO reset. A logic 1 written here will clear all bytes in the transmitter FIFO and reset all of its counter logic to 0. The transmitter shift register is not cleared by this bit. CPC700 User’s Manual—Preliminary...
Page 202: Interrupt Identiﬁcation Register
When the processor accesses the IIR, the UART records new interrupts, but does not change its current contents until the access by the processor is complete. The UART indicates the highest priority interrupt pending to the CPC700 interrupt controller via the IIR. Table 75. Interrupt Identiﬁcation Register Description...
Page 203: Interrupt Enable Register
Three types of UART interrupts are enabled via the interrupt enable register (IER). Any of the three interrupt types can be used to surface a UART interrupt to the CPC700 interrupt controller. Each interrupt type can be enabled by setting its appropriate bit. Resetting bits 4 through 7 of the IER totally disables the UART interrupt system.
Page 204: Scratchpad Register
Baud rate (bits/s) = (CPC700 SYS_CLOCK / 4) / (16 x Decimal Divisor) For example, if the CPC700 SYS_CLOCK = 33.33 MHz and a baud rate of 9600 bits/sec is required: Decimal Divisor = (CPC700 SYS_CLOCK / 4) / (16 x Baud rate)
Page 205: Fifo Operation
FIFO while servicing this interrupt. The transmitter FIFO empty indications are delayed by one character time minus the last stop bit time whenever the following event occurs: THRE = 1 and there were less than two bytes simultaneously present CPC700 User’s Manual—Preliminary 7-11...
Page 206: Polled Mode
7.4 UART Reset and Sleep Mode Both UARTs are reset upon a reset of the CPC700. They can also be reset individually by software via the UART reset bits in the CPRRESET register. They can also be placed in sleep mode via the UART sleep bits in the CPRPMCTRL register.
Page 207: Chapter 8. Iic
C Speciﬁcation, dated 1995. The IIC bus is a two wire, bidirectional, open-drain, low-speed serial interface. Both the serial clock (SCL) and the serial data (SDA) lines are bidirectional to support multiple bus masters, and to mix “fast” and “slow” devices on the same bus. The CPC700’s IIC ®...
Page 208: Iic Register Map
IIC registers are accessed via memory locations 0xFF6X_000Y, where X=2 for the IIC0 interface and X=3 for the IIC1 interface. Y designates the register within the IIC0 or IIC1 interface to be accessed. Table 78. IIC Registers CPC700 Addres Affected by...
Page 209: Iic Register Deﬁnitions
When a master transfer is requested, the IIC interface handles this latency. When the buffer is written with two bytes via one double-byte access, and the FIFO is empty, byte 0, the most signiﬁcant byte CPC700 User’s Manual—Preliminary...
Page 210: Lo Master Address Register
of the halfword written, is put into the ﬁrst stage and byte 1, the least signiﬁcant byte of the halfword writ- ten, is put into the second stage. In this case, byte 0, is sent out to the IIC bus first and byte 1, is sent out second.
Page 211: Control Register
During the transfer, and when the transfer is complete, the status and extended status registers can be read by the program to determine the state of the IIC interface and the IIC bus. See Table 78 “IIC Registers” on page 8-2. CPC700 User’s Manual—Preliminary...
Page 212: Table 83. Control Register
Table 83. Control Register Register ‘FF6X_0006’ - Control bit 0 Halt master transfer. When set to a logic 1, the halt function is performed. If IIC was performing a requested master transfer, it will issue the STOP signal at the earliest possible point on the IIC bus.
Page 213: Mode Control Register
1. bit 5 Enable interrupt. When set to a logic 1, allows an interrupt to be generated to the CPC700 interrupt controller when an event occurs and the event is enabled in the interrupt mask register.
Page 214: Status Register
Table 85. Mode Control Register (Continued) Register ‘FF6X_0007’ - Mode Control bit 6 Exit unknown IIC bus state. When set to a logic 1, the bus control state machine will exit the unknown bus state, if IIC is currently in this state. If IIC is not in the unknown bus state, then setting this bit to a logic 1 has no effect.
Page 215: Extended Status Register Notes
6 IRQ active. When set to a logic 1, an IIC interrupt has been sent to the CPC700 interrupt controller. The extended status and extended control and slave status registers can be read to see why the interrupt was set. The interrupt is cleared by writing a logic 1 to this bit. If interrupts are disabled, bit 5 in the mode control register is logic 0, then this bit, IRQ active, will not be set.
Page 216: Lo Slave Address Register
or if none was present at the time the pending interrupt went to the on-deck state, the on-deck interrupt is moved into the active state. Note that an active interrupt remains in the active state until it is cleared by the program.
Page 217: Hi Slave Address Register
8.4.9 Clock Divide Register This register is used to divide the CPC700 SYS_CLOCK signal to form the base clock that is used for inter- facing to the IIC bus. This register must be programmed before the mode control register. The IIC state machines will not be activated until this register is programmed.
Page 218: Interrupt Mask Register
Table 91. IIC Clock Divide Programming CPC700 SYS_CLOCK Frequency Range (MHz) N (Hex) = 20 20 < ƒ ≤ 30 30 < ƒ ≤ 40 40 < ƒ ≤ 50 50 < ƒ ≤ 60 8.4.10 Interrupt Mask Register This register should be set before interrupts are enabled in the mode control register.
Page 219: Table 93. Transfer Count Register
Care must be used when changing the setting of bit 6, enable pulsed IRQ. If this bit is changed from a logic 1 to a logic 0 while an interrupt is active, the IIC interrupt signal to the CPC700’s interrupt controller will go active.
Page 220: Direct Control Register
This is a read-only bit. bit 6 Enable pulsed IRQ. When set to a logic 1, the IIC_IRQ signal to the CPC700 interrupt controller goes active for one clock period. When set to a logic 0, the IIC_IRQ signal stays active until the IRQ active bit, bit 1 of the status register is cleared.
Page 221: Interrupts
IIC interface registers. All IIC interrupts are capable of triggering an interrupt request to the CPC700’s interrupt controller. If enabled properly in the interrupt controller, an IIC interrupt can be used to interrupt the processor. See Chapter 10., “Interrupt Controller” for additional information.
Page 222: General Considerations
extended control and slave status register when the ﬁrst interrupt occurred. Then, sometime later, the rou- tine wishes to clear this status by writing 0x10 back to the register. If the slave write operation completes in between the time the register is read and written, the register will contain a 0x30 when the 0x10 is written. Since writing a bit to logic 0 has no effect once it is logic 1, the slave write complete status is not lost.
Page 223 If this were to occur, the ﬁrst master would issue a STOP while the second master was sending the MSB of its second data byte. The soft reset bit in the extended control and slave status register should be set if the direct control register is to be used. CPC700 User’s Manual—Preliminary 8-17...
Page 224 8-18...
Page 225: Chapter 9. General Purpose Timers
The General Purpose Timer (GPT) provides a separate time base counter and system timers for the CPC700. Five capture timers and ﬁve compare timers are implemented in the GPT macro. The following sections include a list of major features, an overview, supported conﬁgurability, and register descriptions of the General Purpose Timer core.
Page 226: Programmability
The TBC may be read and written by software using its memory mapped address. The TBC is synchronously reset to zero upon a CPC700 reset or when either the GPT_RST or GPT_TBC_RST bits are set in the CPRRESET register. Refer to Section 6.5.2, “Peripheral Reset Control Register (CPRRESET)”...
Page 227: Capture Timers
Note that the CPRCAPTEVNT register is implemented in the Clock, Power Management, and Reset (CPR) logic of the CPC700. The bits in the CPRCAPTEVNT register can be made falling-edge active (set to 0 to trigger) or rising-edge active (set to 1 to trigger) via the GPT Edge Detection Control (GPTEC) register.
Page 228: Compare Timers
• The corresponding Interrupt Enable bit must be set (1) in the GPT Interrupt Enable (GPTIE) Register. • The corresponding capture event must occur (set via the CPRCAPTEVNT register). • If enabled in the CPC700 interrupt controller, the capture timer interrupt will be sent to the processor. 9.2.3 Compare Timers Each of the ﬁve compare timers (GPTCOMP0-4) is 32 bits wide and provides a reference value which is...
Page 229: Interrupt Generation
• The Time Base Counter must increment to the same value programmed in the corresponding Com- pare Timer (COMPx) Register, excluding Compare Mask (MASKx) Register bits. • If enabled in the CPC700 interrupt controller, the compare timer interrupt will be sent to the processor. 9.2.4 Interrupt Generation The capture and compare interrupts are implemented as ten separate interrupt lines to the CPC700 inter- rupt controller, one for each of the ﬁve capture and ﬁve compare timers.
Page 230: Gpt Detailed Register Description
9.3 GPT Detailed Register Description The following sections provide a complete bit description of the GPT registers. All registers are accessed using their memory mapped addresses as shown in Table 96. The Capture Timer Registers (CAPTx) are read-only. The GPT Interrupt Status (GPTIS) Register bits are either set or cleared when written depend- ing upon which one of two addresses used.
Page 231: Gpt Edge-Detection Control (Gptec) Register
Bits [0:4] map to the corresponding capture timer and capture event signal as deﬁned in the CPR- CAPTEVNT register (see Figure 52). Bits [5:31] are reserved. When zero (0), the non-synchronized path is selected and when one (1), the synchronized path is selected. Using the synchronized path causes an additional cycle delay. CPC700 User’s Manual—Preliminary...
Page 232: Gpt Interrupt Mask (Gptim) Register
Bits in this register mask both the setting of the corresponding GPTIS bits and the interrupt output signals to the CPC700 interrupt controller. If masked, GPTIS bits are not set and interrupt signals are not gener- ated (even if the GPTIE bits are enabled).
Page 233: Gpt Interrupt Enable (Gptie) Register
[16:20], correspond to the compare timer interrupt enable bits (see Figure 55). In order for interrupt signals to be sent to the CPC700 interrupt controller, the interrupt mask (GPTIM) bits must be reset (not masked) and the interrupt enable (GPTIE) bits must be enabled.
Page 234: Gpt Capture Event Generation Register
0 = A comparison is performed 1 = No Comparison is performed. A valid compare is forced for the bit. 9.3.11 GPT Capture Event Generation Register This register is provided to signal events that will cause the capture timers to trigger. System software may set and reset these bits as desired to time certain system events.
Page 235: Chapter 10. Interrupt Controller
Chapter 10. Interrupt Controller 10.1 Introduction The CPC700’s Universal Interrupt Controller (UIC) provides the control, status, and communications nec- essary between the various sources of interrupts and the system microprocessor. Features of the UIC include: • 29 interrupts sources - 12 External Interrupts...
Page 236: Overview
Note that the spacing required between interrupt service routines (512 bytes) when using the generated vector address, is not programmable and can not be changed for the CPC700 UIC. Vectors will only be generated for interrupts programmed as INT, that is, programmed to generate an external interrupt to the processor.
Page 237: Interrupt Assignments
CPC700’s IRQ[0:11] input signals. For example, an active external interrupt connected to the CPC700’s IRQ[0] input pin would be registered as IRQ 20 in the UIC status register. Sensitivity and polarity for the external interrupt inputs are system dependent and should be initialized accordingly.
Page 238: Interrupt Vector Base Address
CPC700’s IRQ_OUT_N output signal to trigger an external interrupt to the processor. MCP pro- grammed interrupts, when properly enabled and when the MCP enable bit (bit 1) of the PRIFOPT1 register is set, will drive the CPC700’s MCP_N output signal to trigger a machine check exception to the processor. 10.4.5 Polarity Each bit of this register is used for determining whether a single interrupt input will be positive active or negative active.
Page 239: Uicsr - Uic Status Register
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Figure 57. UICSRS -- UIC Status Register -- Set CPC700 User’s Manual—Preliminary 10-5...
Page 240: Uicer - Uic Enable Register
MCP programmed interrupts, when properly enabled and when the MCP enable bit (bit 1) of the PRIFOPT1 register is set, will drive the CPC700’s MCP_N output signal to trigger a machine check exception to the processor. The MCP enable bit of the PRIFOPT1 register must be set to enable MCP_N output.
Page 241: Uicpr - Uic Polarity Register
UICPR will cause an interrupt to be detected on a rising edge. Refer to Section 10.3, “Interrupt Assign- ments” for important information on how to program the edge/level trigger register for the CPC700. 10.5.6 UICTR — UIC Trigger Register...
Page 242: Uicmsr - Uic Masked Status Register
10.5.7 UICMSR — UIC Masked Status Register Interrupt [0] Masked Interrupt [1] Masked Interrupt [2] Masked Interrupt [3] Masked Interrupt [4] Masked Interrupt [31] Masked • • • • • • • • • 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Figure 62.
Page 243: Uicvr - Uic Vector Register
A high priority interrupt goes active — the vector changes to the high priority interrupt. The software resets the high priority interrupt — the vector changes to the low priority interrupt. The software resets the enable bit for the low priority interrupt — the vector goes to all 0s. CPC700 User’s Manual—Preliminary 10-9...
Page 244 10-10 Interrupt Controller...
Page 245: Chapter 11. Jtag
Chapter 11. JTAG IEEE 1149.1 (JTAG) Boundary scan is included to facilitate tester requirements as well as for the support of board level testing and debug. The following JTAG commands are supported by the CPC700 JTAG TAP controller: EXTEST SAMPLE / PRELOAD...
Page 246 11-2 JTAG...
Page 247: Chapter 12. Processor Local Bus (Plb)
Access to the PLB is granted through a central arbitration mechanism that enables masters to compete for bus ownership. This arbitration mechanism provides for the implementation of several priority schemes. Table 100 lists the PLB masters provided in the CPC700. Table 100. CPC700 PLB Master Assignments Master ID...
Page 248: Plb Arbiter Registers
12.2 PLB Arbiter Registers PLB arbiter registers are accessed using the addresses in Table 102. Table 102. PLB Arbiter Registers Mnemonic Register Name Address Access PACR PLB Arbiter Control Register 0xFF50_085C PEAR PLB Error Address Register 0xFF50_0858 PESR PLB Error Status Register 0xFF50_0850 R/Clear 12.2.1 PLB Arbiter Control Register (PACR)
Page 249: Plb Error Status Register (Pesr)
Processor Core DCU PESR Field Lock 0 Master 1 PESR ﬁeld is unlocked 1 Master 1 PESR ﬁeld is locked ALK1 Processor Core DCU PEAR Address Lock 0 Master 1 PEAR is unlocked 1 Master 1 PEAR is locked 8:31 Reserved CPC700 User’s Manual—Preliminary 12-3...
Page 250 12-4 Processor Local Bus (PLB)
Page 251: Chapter 13. Opb Bridge
Figure 69. OPB Bridge Error Status Register (GESR) PTE0 PLB Timeout Error Status Master 0 Master 0 is the 60x-PLB processor 00 No master 0 error occurred interface. 01 Master 0 timeout error occurred 10 Master 0 slave error occurred 11 Reserved CPC700 User’s Manual—Preliminary 13-1...
Page 252 R/W0 Read Write Status Master 0 0 Master 0 error operation is a write 1 Master 0 error operation is a read FLK0 GESR Field Lock Master 0 0 Master 0 GESR ﬁeld is unlocked 1 Master 0 GESR ﬁeld is locked ALK0 GEAR Address Lock Master 0 0 Master 0 GEAR address is unlocked...
Page 253: Chapter 14. Register Summary
Chapter 14. Register Summary 14.1 CPC700 Registers Registers within the CPC700 are located according to the following tables. Detailed descriptions may be found in the individual chapters. 14.1.1 Processor Interface Registers Processor interface registers are accessed through an indirect method employing a conﬁguration address register, PIFCFGADR, and a conﬁguration data register, PIFCFGDATA.
Page 254: Memory Controller Registers
Table 103. Offsets for Processor Interface Registers (Continued) Register Offset Description BESRSET PLB Bus Error Syndrome Register Set (for test/veriﬁcation use) Reserved BEAR PLB Bus Master Error Address Register Reserved Reserved PLBSWRINT Write Interrupt Region Base Address 14.1.2 Memory Controller Registers The Memory controller registers are accessed similar to the processor interface registers through an indi- rect address mechanism.
Page 255: Pci Interface Registers
PMM 1 PCI Low Address PMM1PCIHA FF40_001C PMM 1 PCI High Address PMM2LA FF40_0020 PMM 2 Local Address PMM2MA FF40_0024 PMM 2 Mask/Attribute PMM2PCILA FF40_0028 PMM 2 PCI Low Address PMM2PCIHA FF40_002C PMM 2 PCI High Address CPC700 User’s Manual—Preliminary 14-3...
Page 256 Table 106. PCI Interface Registers (Continued) Register Address Description PTM1MS FF40_0030 PTM 1 Memory Size PTM1LA FF40_0034 PTM 1 Local Address PTM2MS FF40_0038 PTM2 Memory Size PTM2LA FF40_003C PTM2 Local Address PCICFGADR FEC0_0000 PCI Conﬁguration Address Register PCICFGDATA FEC0_0004 PCI Conﬁguration Data Register The PCI Interface conﬁguration registers that are accessed through an indirect method employing an address register, PCICFGADR, and a data register, PCICFGDATA are listed in Table 107.
Page 257: Cpr Registers
Strapping Pin Status Read Register 14.1.5 PLB Macro Registers Table 109. PLB Macro Conﬁguration Registers Register Address Description PACR FF50_085C PLB Arbiter Control Register FF50_0858 PEAR PLB Error Address Register PESR FF50_0850 PLB Error Status Register (Read/Clear) CPC700 User’s Manual—Preliminary 14-5...
Page 258: Opb Bridge Macro Registers
14.1.6 OPB Bridge Macro Registers Table 110. OPB Macro Conﬁguration Registers Register Address Description GESR FF50_0810 OPB Bridge Error Status Register (Read/Clear) GEAR FF50_0818 OPB Bridge Error Address Register 14.1.7 Universal Interrupt Controller Registers The following table lists the UIC registers. See Section 10.5, “Universal Interrupt Controller Registers” for detailed register information.
Page 259: Iic1 Registers
IIC1 Low Slave Address IIC1HSADR FF63_000B IIC1 High Slave Address IIC1CLKDIV FF63_000C IIC1 Clock Divide IIC1INTRMSK FF63_000D IIC1 Interrupt Mask IIC1XFRCNT FF63_000E IIC1 Transfer Count IIC1XTCNTLSS FF63_000F IIC1 Extended Control and Slave Status IIC1DIRECTCNTL FF63_0010 IIC1 Direct Control CPC700 User’s Manual—Preliminary 14-7...
Page 260: Uart0 Registers
14.1.10 UART0 Registers The following table lists the UART0 registers. See Section 7.2.1, “UART Register Summary” for detailed register information. Table 114. UART0 Conﬁguration Registers Register Address Description UART0RBR FF60_0300 UART 0 Receiver Buffer Register UART0THR FF60_0300 UART 0 Transmitter Holding Register UART0IER FF60_0301 UART 0 Interrupt Enable Register...
Page 261: Gpt Registers
TBC Mask (Compare Timer 0) GPTMASK1 FF65_00C4 TBC Mask (Compare Timer 1) GPTMASK2 FF65_00C8 TBC Mask (Compare Timer 2) GPTMASK3 FF65_00CC TBC Mask (Compare Timer 3) GPTMASK4 FF65_00D0 TBC Mask (Compare Timer 4) Reserved D4 - FC CPC700 User’s Manual—Preliminary 14-9...
Page 262 14-10 Register Summary...
Page 263: Chapter 15. I/O Driver Speciﬁcations
I/O LVTTL IIC0_SDA I/O LVTTL IIC1_SCL I/O LVTTL IIC1_SDA I/O LVTTL IRQ_IRQ[0:11] LVTTL IRQ_IRQ_OUT_N LVTTL MEM_BA[0:1] LVTTL MEM_BANK_SEL[0:4] LVTTL MEM_CKE LVTTL MEM_DATA[0:63] I/O LVTTL MEM_DQM LVTTL MEM_ECC[0:7] I/O LVTTL MEM_ADDR[0:12] LVTTL MEM_SD_CAS_N LVTTL MEM_SD_RAS_N LVTTL MEM_WE_N LVTTL CPC700 User’s Manual—Preliminary 15-11...
Page 264 Table 116. I/O Driver Speciﬁcations (Continued) Internal Pullup or Input Driver Ioh (mA) Iol (mA) Pulldown Voltage Signal Type Vhigh=2.4V Vlow=0.4V (Ohms) Tolerance (V) PCI_66_STRAP PCI_AD[0:31] I/O PCI note 1 note 1 PCI_CLK PCI_C/BE_N[0:3] I/O PCI note 1 note 1 PCI_DEVSEL_N I/O PCI note 1...
Page 265: Index
PLB arbiter 12-2 line status register 7-6 PLB to OPB bridge 13-1 SPCTL 9-6 Memory Access Arbiter 4-4 SPHS 9-6 Memory Controller 4-1 SPLS 9-9 Memory Interface Singals 2-5 SPRB 9-9 SPRC 9-7, 10-5, 10-6, 10-7, 10-8, 10-9 CPC700 User’s Manual—Preliminary Index-1...
Page 266 SPTB 9-7 Reset 6-1 ROM/Peripheral Controller 4-29 scratchpad register 7-10 SDRAM 4-4 serial port registers 9-1 serial-interface characteristic 7-2 serial-to-parallel conversion 1-8, 7-1 Signal Descriptions 2-1 Snoop Cycles 3-12 SPCTL 9-6 SPHS 9-6 SPLS 9-9 SPRB 9-9 SPRC 9-7, 10-5, 10-6, 10-7, 10-8, 10-9 SPTB 9-7 System Interface Signals 2-7 Test Interface Signals 2-7...
Page 267 CPC700 User’s Manual—Preliminary...
Page 268 States of America February, 2000. All Rights Reserved. IBM Microelectronics, PowerPC, PowerPC 603e, RiscWatch, and AIX are trade- marks of the IBM corporation. IBM and the IBM logo are registered trademarks of the IBM corporation. Other company names and product identifiers are trade- marks of the respective companies.

IBM CPC700 User Manual

Table of Contents

Chapter 1. Introduction

Chapter 2. Signal Descriptions

Chapter 3. Processor Interface

Chapter 4. Memory Controller

Chapter 5. PCI Interface

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Summary of Contents for IBM CPC700