Supported Processor Transfer Types; Table 7. Supported Processor Transfer Type Encodings/Response - IBM CPC700 User Manual

3.5 Supported Processor Transfer Types

Based on signals TT[0:3] (see Table 7), the CPC700 responds to processor initiated transfers by generat-
ing a read transaction, a write transaction, or an address-only response. The CPC700 ignores TT[4] when
evaluating processor initiated transfers.
The CPC700 supports all processor to memory/PLB bursts and all single-beat transfer sizes and alignments
that do not cross a 4-byte boundary. The following table lists all supported processor transfer types and the
corresponding response from the CPC700.
NOTE: In Table 7, SBR is single-beat read and SBW is single-beat write.

Table 7. Supported Processor Transfer Type Encodings/Response

Processor
TT[0:3] Operation
0000 Clean block or lwarx
0001 Write with flush
0010 Flush block or stwcx
0011 Write with kill
0100 sync or tlbsync
0101 Read or read with no
intent to cache
0110 Kill block or icbi
0111 Read with intent to
modify
1000 eieio
1001 Write with flush
atomic, stwcx
1010 ecowx
1011 Reserved
CPC700 User's Manual—Preliminary
Proc Bus CPC700 Response for
Transaction Proc to Memory
Address only Assert AACK_N, No other response, No PLB
transaction
SBW or burst Memory write
Address only Assert AACK_N, No other response, No PLB
transaction
SBW or burst Memory write
Address only Assert AACK_N, No other response
SBR or burst Memory read
Address only Assert AACK_N, No other response, No PLB
transaction
Burst Memory read
Address only Assert AACK_N, No other response
SBW Memory write
SBW Reserved
Assert AACK_N and TA_N. MCP_N asserted if
MCP_N assertion is enabled.
Reserved
Assert AACK_N and TA_N. MCP_N asserted if
MCP_N assertion is enabled.
CPC700 Response for
Proc to PLB
PLB write
PLB write
PLB read
PLB read
PLB write
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