Pci To Memory Byte Swapping Examples; Figure 7. Alternative Byte Swapping Method - IBM CPC700 User Manual

Memory controller and pci bridge
Table of Contents

Advertisement

No address manipulation occurs. As an example, a byte access to memory shared between the local pro-
cessor and the PCI at MEM_BYTE0 must be accessed as Byte 0 by the processor and as Byte 3 by the
PCI device.
When enabled, this swapping will occur on all accesses from the PCI to local memory, independent of the
size of the transfer (1, 2, 3, or 4 bytes).
Processor
(Big-Endian;
msb is bit 0)
PLB Byte Lanes
PCI
(Little-Endian;
msb is bit 31)
Note: As indicated, this swapping occurs only on PCI to local memory accesses. Even if this byte swapping
mechanism is enabled, PCI accesses to CPC700 internal PCI configuration registers are not affected.

3.11.2.3 PCI to Memory Byte Swapping Examples

To illustrate the two methods of byte swapping which may be used for local memory accesses from the PCI
bus, assume the local processor has written a 32-bit value of x'12345678' to local memory. Byte '12' is the
MSB and '78' is the LSB as seen from the local processor.
Using the default "byte lane preservation" method, when the PCI accesses the same memory location, the
value will appear on the PCI bus as x'78563412', where byte '78' is on the PCI bus MSB and '12' is on the
LSB.
Using the alternative "byte lane swapping" method the value on the PCI bus will be x'12345678' where byte
'12' is on the PCI MSB and '78' on the LSB. Since the value is the same as seen from both the local pro-
cessor and the PCI bus, this method can be thought of as a "value preservation" method of byte swapping.
Note: The value preservation only preserves values of 32-bit data quantities. This method of byte swapping
should not be used for data quantities less than 32-bits. The default byte lane preservation method should
be used for transfer sizes other than 32-bit.
3-16
[0:7]
[8:15]
[16:23] [24:31]
0
1
2
0
1
2
3
2
1
[31:24]
[23:16]
[15:8]

Figure 7. Alternative Byte Swapping Method

[32:39] [40:47] [48:55] [56:63]
3
4
5
3
4
5
0
[7:0]
6
7
6
7
Processor Interface

Advertisement

Table of Contents
loading

Table of Contents