Bridge Configuration - IBM CPC700 User Manual

"about" or "an average." This is because the actual penalties are dependent on the frequency ratio between
the PLB bus (60x bus) and the PCI bus, the skew between the two clocks at any instance, and previous
bus activity.
Single processor write to PCI bus
• No change in bus bandwidth. Each transfer takes two PCI clocks minimum.
Back-to-back processor writes to PCI bus
• In synchronous mode, a write can be generated at a maximum of once every three PCI clocks.
• In asynchronous mode, a write can be generated at a maximum of once every five PCI clocks.
Single processor read from PCI bus, non-prefetched
• In asynchronous mode, read latency is increased by an average of five PCI clocks.
Burst processor read from PCI bus, prefetched
In asynchronous mode, the first read reaches the 60x bus an average of five PCI clocks later than in syn-
chronous mode. During burst prefetch in synchronous mode, no master wait states are added (IRDY# is
always active).
In asynchronous mode, one wait state is added (IRDY# pace) after every fourth transfer; thus, maximum
bandwidth is reduced by about 20%.
PCI master write to memory
• In synchronous mode, data is accepted every clock, as long as FIFO is not full (no wait states). If FIFO
fills up, a disconnect occurs.
• In asynchronous mode, one wait state is added after about every fourth transfer, as long as FIFO is not
full; thus, maximum bandwidth is reduced about 20%. Also, disconnects occur more frequently.
PCI master read memory
• In synchronous mode, initial latency is the result of numerous factors, including previously posted
writes to memory, CPU activity, memory speed, memory refresh, and snoop push requirements. When
data is available in sync mode, it is typically passed to the PCI without wait states.
• In asynchronous mode, initial latency is increased an average of five PCI clocks over the sync value,
and one wait state is added after about every fourth transfer; thus, maximum bandwidth is reduced
about 20%. Also, disconnects occur more frequently.
5.9 Bridge Configuration
The CPC700 has two sets of configuration registers for configuring the PCI interface, handling errors, and
reporting status. The Local Configuration Registers control PLB related functions, and can only be
accessed by the processor. The PCI Configuration Registers control PCI related functions, and can be
accessed from both the processor and the PCI.
The registers are all described using Little-Endian bit ordering. Thus the most-significant bit is bit 31, and it
is always shown on the left.
Furthermore, the PCI interface hardware implements the registers in Little-Endian byte ordering. Thus,
software that runs in Big-Endian mode must take this into account when accessing the registers.
CPC700 User's Manual—Preliminary 5-19