IBM CPC700 User Manual page 18

For mission critical, zero down time operations, the CPC700 incorporates Error Correction Code (ECC) cir-
cuitry with the ability to correct data errors as well as detect address errors. The device also supports the
processor's address and data parity scheme. If processor data parity is not required, the unused pins can
be configured to provide PCI arbitration.
A complement of internal peripherals are available, including an interrupt controller, programmable timers,
dual UARTs, and two independent IIC ports. If the design requires additional functionality, an integrated
peripheral bus supports 8-, 16-, 32-, or 64-bit device operations for external peripherals. This bus also sup-
ports the Boot ROM. Additional chip selects are provided to eliminate the need for external glue logic. A
total of five chip selects are provided that may be programmed to support ROM banks, SDRAM banks, or
peripherals, providing a very flexible system environment.
Critical to intelligent embedded applications, the PCI interface offers features that allow the CPC700 to
operate in a host role, as an intelligent add-in card, or in stand-alone operating modes. The following dia-
gram shows the CPC700 in a typical system configuration.
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