Pll Configuration Access Register (Cprpllaccess); Pll Tuning Control Register (Cprplltune); Table 68. Pll Tuning Control Register - IBM CPC700 User Manual

6.5.4 PLL Configuration Access Register (CPRPLLACCESS)
Address: FF50_090Ch
Width: 32 bits
Reset Value: 0000_0000
Access: Read /Write
This register controls access to the PLL Tuning Control register. Setting bit 0 to a "1" allows the PLL Tuning
Control register to be written.
Bit Name
0 PLLWRENABLE
1:31

6.5.5 PLL Tuning Control Register (CPRPLLTUNE)

Address: FF50_0910h
Width: 32 bits
Reset Value: Depends on Strapping bit configuration
(104F_484F - for 25-50MHz PCI bus)
(104F_B44F - for 49-67MHz PCI bus)
Access: Read - Returns the current contents of the register
Write - The act of writing this register will cause an immediate reset on RESET_OUT_N.
See Section 6.1.1, "PLL Tuning" for important information regarding this register.
Bit Name
0:2 PLL0_RANGEA
3:5 PLL0_RANGEB
6:9 PLL0_MULT
10:15 PLL0_TUNE
16:18 PLL1_RANGEA
19:21 PLL1_RANGEB
22:25 PLL1_MULT
26:31 PLL1_TUNE
Note: If changes from the default values are required, contact your IBM representative for proper values for
this register.
6-8
Table 67. PLL Configuration Access Register
Default Description
0 PLL Configuration Register Access Enable
0 Reserved - Reads return 0

Table 68. PLL Tuning Control Register

Default
25-50MHz PCI
000
100
0001
001111
010
010
0001
001111
Default
49-67MHz PCI Description
000 PLL 0 RangeA
100 PLL 0 RangeB
0001 PLL 0 Multiplication Factor
001111 PLL 0 Tuning Bits
101 PLL 1 RangeA
101 PLL 1 RangeB
0001 PLL 1 Multiplication Factor
001111 PLL 1 Tuning Bits
Clock, Power Management, and Reset