Pci Built-In Self Test (Bist) Control; Pci Base Address Register 0 (Pcibar0); Pci Base Address Register 1 (Pciptm1Bar); Table 52.Pci Bar 1 - IBM CPC700 User Manual

5.9.3.10 PCI Built-in Self Test (BIST) Control

Address offset: 0Fh
Width: 8
Reset Value: 00h
Access: Read
The PCI BIST register is used for control and status of BIST. The CPC700 does not implement BIST, there-
fore this register is read-only and returns 00h when read.

5.9.3.11 PCI Base Address Register 0 (PCIBAR0)

Address offset: 10h
Width: 32 bits
Reset Value: 0000_0000h
Access: Read
BAR 0 is unimplemented, and always returns ZERO when read.

5.9.3.12 PCI Base Address Register 1 (PCIPTM1BAR)

Address offset: 14h
Width: 32 bits
Reset Value: 0000_0008h
Access: Read/Write
This register defines a space in PCI Memory space that is mapped to PLB space (system memory or
ROM). For more information, see Table 52..
Bit(s) Name
0 Memory Space Indi-
cator
2:1 Location Type
3 Prefetchable
11:4 Base Address -
always zero
5-32

Table 52.PCI BAR 1

Description
This bit is always 0 to indicate Memory space (rather than I/O).
These bits are always 00 to indicate that the memory space can be
located anywhere in the 32-bit address space.
This bit is always 1 to indicate that prefetching is allowed.
These bits are always 0 since the minimum size of this range is 4k
bytes.
PCI Interface