Mode Control Register; Table 85. Mode Control Register - IBM CPC700 User Manual

not Ack = IIC "not acknowledge" signal sent if doing a read
Wait = IIC interface goes to wait state
Pause = IIC interface goes to pause state
Strt? = IIC "start" signal sent, if IIC interface was stopped or waiting
Stop = IIC "stop" signal sent, IIC interface goes to stopped state
Xfr = Requested bytes are transferred
Halt overrides the chain and repeated start bits.
Repeated start with pending transfer overrides the chain bit.

8.4.4 Mode Control Register

In typical applications, this register is programmed only once in the program's initialization routine. Applica-
tions that include complex error handling might reprogram this register more often. The clock divide regis-
ter must be programmed before this register is programmed. The Lo and Hi slave address registers should
also be programmed before this register is programmed.
You must take into account the fact that the IIC interface does not implement any timeout functions for com-
munications on the IIC bus. Any such function, if needed, must be implemented using the IIC halt function,
the soft reset function via the Extended Control and Slave Status register, or an IIC reset via the CPRRE-
SET register (see Section 6.5.2, "Peripheral Reset Control Register (CPRRESET)" ).
With regards to bit 7 of the Mode Control register, a slave not ready condition is defined in a slave receive
operation as a slave having no free space in its slave data buffer at the start of the write operation, or that
the slave data buffer has gone full during the write operation. A slave not ready condition is defined in a
slave transmit operation as a slave having no data in its slave data buffer at the start of the read operation,
or that the slave data buffer has gone empty during the read operation.
How the IIC interface handles not ready conditions can potentially affect system performance. A slave that
holds SCL low is a slave that guarantees data delivery to or from the requesting master. However, a slave
that holds SCL low is also one that prevents other masters from performing transfers over the IIC bus. In
general, there is no fixed rule on how this should be handled; each system will have its own unique consid-
erations.
bit 0 Flush slave data buffer. When set to a logic 1, the slave data buffer will be set to empty. This
bit will be cleared once the buffer has been emptied.
bit 1 Flush master data buffer. When set to a logic 1, the master data buffer will be set to empty.
This bit will be cleared once the buffer has been emptied.
bit 2 Enable general call. When set to a logic 1, IIC will respond to a general call on the IIC bus.
Note that enable slave mode overrides this bit. If enable slave mode is logic 0, a general call
will be ignored.
bit 3 Fast/standard mode. When set to a logic 1, IIC will transfer data at a rate of 400 kHz (fast
mode). When set to a logic 0, IIC will transfer data at a rate of 100 kHz (standard mode).
bit 4 Enable slave mode. When set to a logic 1, slave transfers are enabled. When set to a logic 0,
IIC will not respond to any slave transfers on the IIC bus. The slave address registers should
be programmed before this bit is set to a logic 1.
bit 5 Enable interrupt. When set to a logic 1, allows an interrupt to be generated to the CPC700
interrupt controller when an event occurs and the event is enabled in the interrupt mask
register. Refer to the interrupt mask register for a list of the events that can generate an
interrupt. When set to a logic 0, the interrupt is disabled.
CPC700 User's Manual—Preliminary

Table 85. Mode Control Register

Register 'FF6X_0007' - Mode Control
8-7