IBM CPC700 User Manual page 23

- PCI master 64 byte read prefetch buffer
• Error tracking/status
• Internal PCI bus arbiter for up to six external devices at PCI bus speeds up to 33MHz. Internal arbiter
use is optional and may be disabled for systems which employ an external arbiter.
• Support for synchronous and asynchronous clocking between Processor and PCI busses. Support for
synchronous clocking is limited to a 33MHz PCI bus operation.
Memory Controller
The CPC700 Memory Controller provides the local PowerPC processor with a low latency access path to
local memory and external peripherals. In addition, it supports hardware coherent accesses to the proces-
sor's local memory from the PCI bus. Coherency is maintained on PCI accesses to local memory by
snooping the processor's L1 cache and posted write buffers before allowing the PCI interface to complete
the requested access.
Industry standard 72-pin and 168-pin modules are supported, allowing for a variety of system memory con-
figurations. The memory controller supports up to five banks (five Chip Select outputs). Bank 0 is dedi-
cated to Boot ROM, while banks 1-4 may be programmed to support either SDRAM, ROM, SRAM, or
external peripherals. Up to 512 MBytes per bank, are supported up to a maximum of 2 GBytes. Memory
timings, starting and ending address ranges, and memory addressing modes are programmable. During
reset, Bank 0 defaults to ROM and is enabled while all other banks are disabled.
Synchronous DRAM:
• Up to 4 banks (Bank 0 defaults to ROM).
• 11x9 to 13x11 addressing for SDRAM (2 and 4 bank internal SDRAM chip architecture supported).
• 8 MByte to 512 MByte per bank.
• Programmable timings and address mapping.
• CAS before RAS refresh w/programmable refresh timer.
• Supports hardware coherency.
• Page mode accesses.
• Sync DRAM configuration via mode set command.
• Memory bus operates at same frequency as processor bus.
• 64-bit and 32-bit memory interface options (72-bit or 40-bit if implementing ECC).
• Support for auto-precharge.
• Support for SRAM self-refresh mode (bank 4 only).
ROM/Peripheral:
• ROM, EPROM, SRAM, and Peripherals supported.
• Burst and Non-Burst devices.
• 1-5 banks (shared with SDRAM).
• 8-, 16-, 32-, and 64-bit data bus widths supported.
CPC700 User's Manual—Preliminary 1-7